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1. 发明申请

WO03043057B1 SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS 审中-公开
标题翻译：基于适当使用电感效应的综合策略
公开(公告)号：WO03043057B1
公开(公告)日：2003-10-30
申请号：PCT/US0236342
申请日：2002-11-12
申请人： MENTOR GRAPHICS CORP , SUAYA ROBERTO , ESCOVAR RAFAEL
发明人： SUAYA ROBERTO , ESCOVAR RAFAEL
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5077 , G06F17/5036
摘要： A method of optimizing the propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed . The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires. The disclose method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedance at the junctions between the branches are substantially equal.
摘要翻译：提供了一种优化布线布局上的传播速度的方法。通常，该方法考虑并使用由平行接地线包围的信号线上的高速信号传播引起的电感效应。具体而言，可以调整限定布线布局的物理参数之一，以在布线布局中创建最大化信号传播速度的rlc关系。被调整的物理参数可以是例如信号线和地线之间的线分离。所公开的方法也可以应用于具有多个分支的布线布局，例如时钟树。在这种情况下，可以使用所公开的方法优化第一分支。然后可以调整下游分支，使得分支之间的连接处的阻抗基本相等。

2. 发明申请

WO2003043057A2 SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS 审中-公开
标题翻译：基于适当使用电感效应的合成策略
公开(公告)号：WO2003043057A2
公开(公告)日：2003-05-22
申请号：PCT/US2002/036342
申请日：2002-11-12
申请人： MENTOR GRAPHICS CORPORATION , SUAYA, Roberto , ESCOVAR, Rafael
发明人： SUAYA, Roberto , ESCOVAR, Rafael
IPC分类号： H01L
CPC分类号： G06F17/5077 , G06F17/5036
摘要： A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal.
摘要翻译：提供了一种优化布线布局的传播速度的方法。通常，该方法考虑并使用由并联接地线包围的信号线上的高速信号的传播引起的电感效应。特别地，可以调整限定布线布局的物理参数之一，以在布线布局中产生使信号传播速度最大化的rlc关系。调整的物理参数可以是例如信号线和接地线之间的线间隔。公开的方法也可以应用于具有多个分支（例如时钟树）的布线布局。在此上下文中，可以使用所公开的方法来优化第一分支。然后可以调节下行分支，使得分支之间的结处的阻抗基本相等。

3. 发明申请

WO2003043057A3 SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS 审中-公开
公开(公告)号：WO2003043057A3
公开(公告)日：2003-05-22
申请号：PCT/US2002/036342
申请日：2002-11-12
申请人： MENTOR GRAPHICS CORPORATION , SUAYA, Roberto , ESCOVAR, Rafael
发明人： SUAYA, Roberto , ESCOVAR, Rafael
IPC分类号： G06F17/50
摘要： A method of optimizing the propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed . The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires. The disclose method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedance at the junctions between the branches are substantially equal.

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