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1. 发明申请

WO2012141859A2 CASCODE SWITCHES INCLUDING NORMALLY-OFF AND NORMALLY-ON DEVICES AND CIRCUITS COMPRISING THE SWITCHES 审中-公开
标题翻译： CASCODE开关，包括正常关闭和正常设备和包含开关的电路
公开(公告)号：WO2012141859A2
公开(公告)日：2012-10-18
申请号：PCT/US2012/030045
申请日：2012-03-22
申请人： SS SC IP, LLC , SPRINGETT, Nigel
发明人： SPRINGETT, Nigel
IPC分类号： H03K17/687 , H03K17/74
CPC分类号： H03K17/168 , H03K17/04206 , H03K17/161 , H03K17/567 , H03K17/687 , H03K17/6871 , H03K2017/6875
摘要： Switches comprising a normally-off semiconductor device and a normally-on semiconductor device in cascode arrangement are described. The switches include a capacitor connected between the gate of the normally-on device and the source of the normally-off device. The switches may also include a zener diode connected in parallel with the capacitor between the gate of the normally-on device and the source of the normally-off device. The switches may also include a pair of zener diodes in series opposing arrangement between the gate and source of the normally-off device. Switches comprising multiple normally-on and/or multiple normally-off devices are also described. The normally-on device can be a JFET such as a SiC JFET. The normally-off device can be a MOSFET such as a Si MOSFET. The normally-on device can be a high voltage device and the normally-off device can be a low voltage device. Circuits comprising the switches are also described.
摘要翻译：描述了包括常闭半导体器件和共模共栅放大的常规半导体器件的开关。开关包括连接在常开装置的栅极和常断装置的源之间的电容器。开关还可以包括在常开器件的栅极和常断器件的源极之间并联连接的齐纳二极管。这些开关还可以包括一对齐纳二极管，它们在常闭装置的栅极和源极之间相对布置。还描述了包括多个常开和/或多个常闭设备的开关。常开器件可以是诸如SiC JFET的JFET。常关器件可以是诸如Si MOSFET的MOSFET。常开设备可以是高压设备，常闭设备可以是低电压设备。还描述了包括开关的电路。

2. 发明申请

WO2011149768A2 SELF-ALIGNED SEMICONDUCTOR DEVICES WITH REDUCED GATE-SOURCE LEAKAGE UNDER REVERSE BIAS AND METHODS OF MAKING 审中-公开
标题翻译：具有降低门极泄漏的自对准半导体器件，具有反向偏置和制造方法
公开(公告)号：WO2011149768A2
公开(公告)日：2011-12-01
申请号：PCT/US2011037275
申请日：2011-05-20
申请人： SS SC IP LLC , RITENOUR ANDREW , SHERIDAN DAVID C
发明人： RITENOUR ANDREW , SHERIDAN DAVID C
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/8083 , H01L29/0657 , H01L29/1066 , H01L29/1608 , H01L29/66068 , H01L29/66909 , H01L29/7722
摘要： A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self- aligned to within 0.5 um to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.
摘要翻译：描述了具有自对准引脚，p + / n / n +或p + / p / n +栅 - 源极结的垂直结型场效应晶体管（VJFET）。为了保持良好的高电压性能（即低DIBL），器件栅极可自动对准至0.5μm以内，同时减少反向偏压下的栅 - 源结泄漏。该器件可以是宽带隙半导体器件，例如SiC垂直沟道结场效应。还描述了制造该装置的方法。

3. 发明申请

WO2012145147A3 VERTICAL JUNCTION FIELD EFFECT TRANSISTORS WITH IMPROVED THERMAL CHARACTERISTICS AND METHODS OF MAKING 审中-公开
标题翻译：具有改进的热特性的垂直连接场效应晶体管及其制造方法
公开(公告)号：WO2012145147A3
公开(公告)日：2013-02-28
申请号：PCT/US2012031505
申请日：2012-03-30
申请人： SS SC IP LLC , CASADY JANNA , CASADY JEFFREY , CHATTY KIRAN , SHERIDAN DAVID , RITENOUR ANDREW
发明人： CASADY JANNA , CASADY JEFFREY , CHATTY KIRAN , SHERIDAN DAVID , RITENOUR ANDREW
IPC分类号： H01L21/335
CPC分类号： H01L29/8083 , H01L29/1608 , H01L29/402 , H01L29/66909
摘要： Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.
摘要翻译：描述了在高电流下具有改进的散热的垂直结型场效应晶体管（VJFET），同时保持了具有小间距长度的器件所需的特定导通电阻和归一化饱和漏极电流特性。 VJFET包括与器件的源极金属电接触的一个或多个电活性源极区域和不与器件的源极金属电接触的一个或多个不活跃电源区域。电流不稳定的源区域在电流流动期间耗散由电活性源区域产生的热量。

4. 发明申请

WO2012141859A3 CASCODE SWITCHES INCLUDING NORMALLY-OFF AND NORMALLY-ON DEVICES AND CIRCUITS COMPRISING THE SWITCHES 审中-公开
标题翻译： CASCODE开关，包括正常关闭和正常设备和包含开关的电路
公开(公告)号：WO2012141859A3
公开(公告)日：2013-01-03
申请号：PCT/US2012030045
申请日：2012-03-22
申请人： SS SC IP LLC , SPRINGETT NIGEL
发明人： SPRINGETT NIGEL
IPC分类号： H03K17/687 , H03K17/74
CPC分类号： H03K17/168 , H03K17/04206 , H03K17/161 , H03K17/567 , H03K17/687 , H03K17/6871 , H03K2017/6875
摘要： Switches comprising a normally-off semiconductor device and a normally-on semiconductor device in cascode arrangement are described. The switches include a capacitor connected between the gate of the normally-on device and the source of the normally-off device. The switches may also include a zener diode connected in parallel with the capacitor between the gate of the normally-on device and the source of the normally-off device. The switches may also include a pair of zener diodes in series opposing arrangement between the gate and source of the normally-off device. Switches comprising multiple normally-on and/or multiple normally-off devices are also described. The normally-on device can be a JFET such as a SiC JFET. The normally-off device can be a MOSFET such as a Si MOSFET. The normally-on device can be a high voltage device and the normally-off device can be a low voltage device. Circuits comprising the switches are also described.
摘要翻译：描述了包括常闭半导体器件和共模共栅放大的常规半导体器件的开关。开关包括连接在常开装置的栅极和常断装置的源之间的电容器。开关还可以包括在常开器件的栅极和常断器件的源极之间并联连接的齐纳二极管。这些开关还可以包括一对齐纳二极管，它们在常闭装置的栅极和源极之间相对布置。还描述了包括多个常开和/或多个常闭设备的开关。常开器件可以是诸如SiC JFET的JFET。常关器件可以是诸如Si MOSFET的MOSFET。常开设备可以是高压设备，常闭设备可以是低电压设备。还描述了包括开关的电路。

5. 发明申请

WO2011149768A3 SELF-ALIGNED SEMICONDUCTOR DEVICES WITH REDUCED GATE-SOURCE LEAKAGE UNDER REVERSE BIAS AND METHODS OF MAKING 审中-公开
公开(公告)号：WO2011149768A3
公开(公告)日：2011-12-01
申请号：PCT/US2011/037275
申请日：2011-05-20
申请人： SS SC IP, LLC , RITENOUR, Andrew , SHERIDAN, David C.
发明人： RITENOUR, Andrew , SHERIDAN, David C.
IPC分类号： H01L29/78 , H01L21/336
摘要： A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self- aligned to within 0.5 um to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.

6. 发明申请

WO2012145147A2 VERTICAL JUNCTION FIELD EFFECT TRANSISTORS WITH IMPROVED THERMAL CHARACTERISTICS AND METHODS OF MAKING 审中-公开
标题翻译：具有改进的热特性的垂直连接场效应晶体管及其制造方法
公开(公告)号：WO2012145147A2
公开(公告)日：2012-10-26
申请号：PCT/US2012/031505
申请日：2012-03-30
申请人： SS SC IP, LLC , CASADY, Janna , CASADY, Jeffrey , CHATTY, Kiran , SHERIDAN, David , RITENOUR, Andrew
发明人： CASADY, Janna , CASADY, Jeffrey , CHATTY, Kiran , SHERIDAN, David , RITENOUR, Andrew
IPC分类号： H01L21/335
CPC分类号： H01L29/8083 , H01L29/1608 , H01L29/402 , H01L29/66909
摘要： Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.
摘要翻译：描述了在高电流下具有改进的散热的垂直结型场效应晶体管（VJFET），同时保持了具有小间距长度的器件所需的特定导通电阻和归一化饱和漏极电流特性。 VJFET包括与器件的源极金属电接触的一个或多个电活性源极区域和不与器件的源极金属电接触的一个或多个不活跃电源区域。电流不稳定的源区域在电流流动期间耗散由电活性源区域产生的热量。

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