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1. 发明申请

WO2010071723A1 SYSTEM AND METHOD FOR RINSE OPTIMIZATION 审中-公开
标题翻译：系统和方法优化RINSE
公开(公告)号：WO2010071723A1
公开(公告)日：2010-06-24
申请号：PCT/US2009/064959
申请日：2009-11-18
申请人： TOKYO ELECTRON LIMITED , PRINTZ, Wallace, P. , SCHEER, Steven
发明人： PRINTZ, Wallace, P. , SCHEER, Steven
IPC分类号： B08B3/00
CPC分类号： H01L21/67051 , H01L21/67028 , H01L21/67253 , H01L22/12 , H01L22/20
摘要： Embodiments of the invention provide optimized rinse systems and methods for providing rinsing solutions to one or more surfaces of semiconductor wafers. Embodiments of the invention may be applied to process wafers at different points in a manufacturing cycle, and the wafers can include one or more metal layers.
摘要翻译：本发明的实施方案提供了优化的冲洗系统和用于向半导体晶片的一个或多个表面提供冲洗溶液的方法。本发明的实施例可以应用于在制造周期中的不同点处理晶片，并且晶片可以包括一个或多个金属层。

2. 发明申请

WO2010033720A1 DUAL TONE DEVELOPMENT PROCESSES 审中-公开
标题翻译：双音发展过程
公开(公告)号：WO2010033720A1
公开(公告)日：2010-03-25
申请号：PCT/US2009/057342
申请日：2009-09-17
申请人： TOKYO ELECTRON LIMITED , FONSECA, Carlos, A. , SOMERVELL, Mark , SCHEER, Steven
发明人： FONSECA, Carlos, A. , SOMERVELL, Mark , SCHEER, Steven
IPC分类号： G03F7/00
CPC分类号： G03F7/095 , G03F7/322 , G03F7/325
摘要： A method and system for patterning a substrate using a dual-tone development process is described. The method and system comprise using a resist material having a polymer backbone with a plurality of protecting groups attached thereto to improve process latitude and critical dimension uniformity for the dual-tone development process. The method can advantageously comprise monitoring various metrics of the subject resists in comparison with simulated limits, enabling corrective changes in process parameters that reduce unwanted variations in product metrics. The system can advantageously comprise an interface layer under or a protecting layer over the resist layer, wherein the interface or protecting layer can be activated to modify the threshold reactivity profile of the resist layer.
摘要翻译：描述了使用双色调显影处理图案化衬底的方法和系统。该方法和系统包括使用具有聚合物主链的抗蚀剂材料，其具有连接到其上的多个保护基，以改善双音发展过程的工艺范围和临界尺寸的一致性。该方法可以有利地包括与模拟限制相比监测受试者抗蚀剂的各种度量，使得能够减少过程参数的校正改变，从而减少产品度量的不期望的变化。该系统可以有利地包括在抗蚀剂层上的保护层下面的界面层，其中该界面或保护层可被激活以修饰抗蚀剂层的阈值反应性分布。

3. 发明申请

WO2007124155A2 OPTIMIZED CHARACTERIZATION OF WAFER STRUCTURES FOR OPTICAL METROLOGY 审中-公开
标题翻译：光学计量学波形结构的优化特征
公开(公告)号：WO2007124155A2
公开(公告)日：2007-11-01
申请号：PCT/US2007/009832
申请日：2007-04-23
申请人： TOKYO ELECTRON LIMITED , SCHEER, Steven , NOLET, Alan , MADRIAGA, Manuel
发明人： SCHEER, Steven , NOLET, Alan , MADRIAGA, Manuel
IPC分类号： G06F19/00
CPC分类号： G01N21/4788 , G03F7/70625
摘要： A patterned structure in a wafer is created using one or more fabrication treatment processes. The patterned structure has a treated and an untreated portion. One or more diffraction sensitivity enhancement techniques are applied to the structure, the one or more diffraction sensitivity enhancement techniques adjusting one or more properties of the patterned structure to enhance diffraction contrast between the treated portion and untreated portions. A first diffraction signal is measured off an unpatterned structure on the wafer using an optical metrology device. A second diffraction signal is measured off the patterned structure on the wafer using the optical metrology device. One or more diffraction sensitivity enhancement techniques are selected based on comparisons of the first and second diffraction signals.
摘要翻译：使用一个或多个制造处理工艺制造晶片中的图案化结构。图案化结构具有经处理和未处理的部分。将一种或多种衍射灵敏度增强技术应用于该结构，一种或多种衍射灵敏度增强技术调整图案化结构的一个或多个性质以增强经处理部分和未处理部分之间的衍射对比度。使用光学测量装置从晶片上的未图案化结构测量第一衍射信号。使用光学测量装置从晶片上的图案化结构测量第二衍射信号。基于第一和第二衍射信号的比较来选择一种或多种衍射灵敏度增强技术。

4. 发明申请

WO2010126735A1 FLOOD EXPOSURE PROCESS FOR DUAL TONE DEVELOPMENT IN LITHOGRAPHIC APPLICATIONS 审中-公开
标题翻译：用于岩石应用中双色发展的FLOOD曝光过程
公开(公告)号：WO2010126735A1
公开(公告)日：2010-11-04
申请号：PCT/US2010/031607
申请日：2010-04-19
申请人： TOKYO ELECTRON LIMITED , FONSECA, Carlos, A. , SOMERVELL, Mark , SCHEER, Steven , PRINTZ, Wallace, P.
发明人： FONSECA, Carlos, A. , SOMERVELL, Mark , SCHEER, Steven , PRINTZ, Wallace, P.
IPC分类号： A61N5/06
CPC分类号： G03F7/30 , G03F7/095 , G03F7/70466
摘要： A method and system for patterning a substrate using a dual tone development process is described. The method and system comprise a flood exposure of the substrate to improve process latitude for the dual tone development process.
摘要翻译：描述了使用双色调显影处理来图案化衬底的方法和系统。该方法和系统包括基底的暴露以提高双音发展过程的过程纬度。

5. 发明申请

WO2010025198A1 METHOD OF PATTERNING A SUBSTRATE USING DUAL TONE DEVELOPMENT 审中-公开
标题翻译：使用双音发展绘制基板的方法
公开(公告)号：WO2010025198A1
公开(公告)日：2010-03-04
申请号：PCT/US2009/055084
申请日：2009-08-26
申请人： TOKYO ELECTRON LIMITED , GRONHEID, Roel , BERNARD, Sophie , FONSECA, Carlos, A. , SOMERVELL, Mark , SCHEER, Steven , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC) VZW , KATHOLIEKE UNVERSITEIT LEUVEN, K.U. LEUVEN R&D
发明人： GRONHEID, Roel , BERNARD, Sophie , FONSECA, Carlos, A. , SOMERVELL, Mark , SCHEER, Steven
IPC分类号： G03C5/00 , G03F9/00
CPC分类号： G03F7/325 , G03F7/2002 , G03F7/322 , G03F7/38
摘要： A method for patterning a substrate is described. In particular, the invention relates to a method for double patterning a substrate using dual tone development. Further, the invention relates to optimizing a dual tone development process.
摘要翻译：描述了用于图案化衬底的方法。特别地，本发明涉及一种使用双音发展对基片进行双重图案化的方法。此外，本发明涉及优化双音发展过程。

6. 发明申请

WO2010114716A1 USING ELECTRIC-FIELD DIRECTED POST-EXPOSURE BAKE FOR DOUBLE PATTERNING (D-P) 审中-公开
标题翻译：使用电场指向的曝光后双面打印纸（D-P）
公开(公告)号：WO2010114716A1
公开(公告)日：2010-10-07
申请号：PCT/US2010/027874
申请日：2010-03-18
申请人： TOKYO ELECTRON LIMITED , SCHEER, Steven , SOMERVELL, Mark
发明人： SCHEER, Steven , SOMERVELL, Mark
IPC分类号： H01L21/461
CPC分类号： H01L21/0332 , H01L21/0337
摘要： The invention provides a method of processing a substrate using Double-Patterning (D-P) processing sequences and Electric-Field Enhanced Layers (E-FELs). The D-P processing sequences and E-FELs can be used to create lines, trenches, vias, spacers, contacts, and gate structures using a minimum number of etch processes.
摘要翻译：本发明提供使用双图案（D-P）处理序列和电场增强层（E-FEL）处理衬底的方法。 D-P处理序列和E-FEL可以用于使用最少数量的蚀刻工艺来产生线，沟槽，通孔，间隔物，接触和栅极结构。

7. 发明申请

WO2007124155A3 OPTIMIZED CHARACTERIZATION OF WAFER STRUCTURES FOR OPTICAL METROLOGY 审中-公开
标题翻译：光学计量学波形结构的优化特征
公开(公告)号：WO2007124155A3
公开(公告)日：2008-11-13
申请号：PCT/US2007009832
申请日：2007-04-23
申请人： TOKYO ELECTRON LTD , SCHEER STEVEN , NOLET ALAN , MADRIAGA MANUEL
发明人： SCHEER STEVEN , NOLET ALAN , MADRIAGA MANUEL
IPC分类号： G06F19/00
CPC分类号： G01N21/4788 , G03F7/70625
摘要： A patterned structure in a wafer is created using one or more fabrication treatment processes. The patterned structure has a treated and an untreated portion. One or more diffraction sensitivity enhancement techniques are applied to the structure, the one or more diffraction sensitivity enhancement techniques adjusting one or more properties of the patterned structure to enhance diffraction contrast between the treated portion and untreated portions. A first diffraction signal is measured off an unpatterned structure on the wafer using an optical metrology device. A second diffraction signal is measured off the patterned structure on the wafer using the optical metrology device. One or more diffraction sensitivity enhancement techniques are selected based on comparisons of the first and second diffraction signals.
摘要翻译：使用一个或多个制造处理工艺制造晶片中的图案化结构。图案化结构具有经处理和未处理的部分。将一种或多种衍射灵敏度增强技术应用于该结构，一种或多种衍射灵敏度增强技术调整图案化结构的一个或多个性质以增强经处理部分和未处理部分之间的衍射对比度。使用光学测量装置从晶片上的未图案化结构测量第一衍射信号。使用光学测量装置从晶片上的图案化结构测量第二衍射信号。基于第一和第二衍射信号的比较来选择一种或多种衍射灵敏度增强技术。

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