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1. 发明申请

WO2004073041A2 TESTING EMBEDDED MEMORIES IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在一体化电路中测试嵌入式存储器
公开(公告)号：WO2004073041A2
公开(公告)日：2004-08-26
申请号：PCT/US2004/004231
申请日：2004-02-13
申请人： MENTOR GRAPHICS CORPORATION , ROSS, Don, E. , DU, Xiaogang , CHENG, Wu-Tung , RAYHAWK, Joseph, C.
发明人： ROSS, Don, E. , DU, Xiaogang , CHENG, Wu-Tung , RAYHAWK, Joseph, C.
IPC分类号： H01L
CPC分类号： G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要： Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation ("EDA") software tool.
摘要翻译：公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。该示例性实施例包括输入逻辑，其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径，存储器内置自检（MBIST）控制器，以及耦合在输入逻辑和 MBIST控制器。本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。在存储器测试模式下，扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中，可以设计，模拟和/或验证任何公开的装置（并且可以执行任何公开的方法）。

2. 发明申请

WO2004073041A3 TESTING EMBEDDED MEMORIES IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在一体化电路中测试嵌入式存储器
公开(公告)号：WO2004073041A3
公开(公告)日：2007-11-29
申请号：PCT/US2004004231
申请日：2004-02-13
申请人： MENTOR GRAPHICS CORP , ROSS DON E , DU XIAOGANG , CHENG WU-TUNG , RAYHAWK JOSEPH C
发明人： ROSS DON E , DU XIAOGANG , CHENG WU-TUNG , RAYHAWK JOSEPH C
IPC分类号： G01R31/28 , G11C29/48
CPC分类号： G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要： One of the disclosed embodiments is an apparatus for testing an embedded memory (202) in an integrated circuit (200). This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller (204), and at least one scan cell (220) coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation ("EDA") software tool.
摘要翻译：所公开的实施例之一是用于测试集成电路（200）中的嵌入式存储器（202）的装置。该示例性实施例包括输入逻辑，其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径，存储器内置自检（MBIST）控制器（204）和至少一个扫描单元（220）耦合在输入逻辑和MBIST控制器之间。本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。在存储器测试模式下，扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中，可以设计，模拟和/或验证任何公开的装置（并且可以执行任何公开的方法）。

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