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1. 发明申请

WO2009144658A1 POWER SWITCH DESIGN METHOD AND PROGRAM 审中-公开
标题翻译：电源开关设计方法与程序
公开(公告)号：WO2009144658A1
公开(公告)日：2009-12-03
申请号：PCT/IB2009/052181
申请日：2009-05-25
申请人： NXP B.V. , PINEDA DE GYVEZ, Jose de Jesus , MEIJER, Rinze Ida Mechtildis Peter , GROOT, Cas
发明人： PINEDA DE GYVEZ, Jose de Jesus , MEIJER, Rinze Ida Mechtildis Peter , GROOT, Cas
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of designing a power switch block (200) for an integrated circuit layout in a predefined integrated circuit technology is disclosed. The power switch block (200) includes a segment (710) comprising a plurality of spaced parallel conductors (110, 120, 130, 140) each having a predefined height in said technology, a stack of a first power switch (115) of a first conductivity type and a pair of drivers (152; 154) for respectively driving the first power switch (115) and a second power switch (135), said drivers having predefined dimensions in said technology, and the second switch (135) of a second conductivity type. The method comprises providing respective predefined width/length ratios for said power switches (115; 135); determining a total height of the segment (710) from the sum of the predefined heights of the individual conductors (110; 120; 130; 140) and respective spacings (310; 320) between said individual conductors, determining the height of the first transistor (115) from the difference between the total height and the predefined driver height; determining the width of the first transistor (115) from the combined predefined widths of the pair of drivers (152; 154); optimizing the first power switch layout within its determined height and width based on its predefined width/length ratio; and optimizing the second power switch layout based on its predefined width/height ratio.
摘要翻译：公开了一种在预定义的集成电路技术中设计用于集成电路布局的功率开关块（200）的方法。功率开关块（200）包括一个段（710），其包括多个间隔开的平行导体（110,120,130,140），每个导体在所述技术中具有预定高度，第一电源开关（115）第一导电类型和用于分别驱动第一电力开关（115）和第二电力开关（135）的一对驱动器（152; 154），所述驱动器在所述技术中具有预定尺寸，并且第二开关（135）第二导电类型。该方法包括为所述功率开关（115; 135）提供相应的预定宽度/长度比; 从各个导体（110; 120; 130; 140）的预定高度和各个导体之间的相应间隔（310; 320）的总和确定段（710）的总高度，确定第一晶体管（115）从总高度和预定义的驾驶员高度之间的差异; 从所述一对驱动器（152; 154）的组合的预定宽度确定所述第一晶体管（115）的宽度; 基于其预定的宽度/长度比，在其确定的高度和宽度内优化第一功率开关布局; 并基于其预定义的宽/高比优化第二功率开关布局。

2. 发明申请

WO2009004535A3 STATIC MEMORY DEVICES 审中-公开
标题翻译：静态存储器件
公开(公告)号：WO2009004535A3
公开(公告)日：2009-02-19
申请号：PCT/IB2008052544
申请日：2008-06-25
申请人： NXP BV , ELVIRA VILLAGRA LUIS , MEIJER RINZE I M , PINEDA DE GYVEZ JOSE DE JESUS
发明人： ELVIRA VILLAGRA LUIS , MEIJER RINZE I M , PINEDA DE GYVEZ JOSE DE JESUS
IPC分类号： G11C11/412 , G11C11/417
CPC分类号： G11C11/413 , H01L27/0207 , H01L27/105
摘要： A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve readingand writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.
摘要翻译：半导体存储器件包括用于构成多个存储单元元件（40）的n阱（22）和p阱（24）。 n阱（22）和p-5阱（24）可以被反向偏置，以提高读取和写入性能。 n阱和p阱中的一个可以是全局偏置的，而n阱和p阱中的另一个可以被诸如块，行或列的组偏置。可以通过调整井偏压来执行误差减小和/或校正。

3. 发明申请

WO2007049210A2 ANALOG IC HAVING TEST ARRANGEMENT AND TEST METHOD FOR SUCH AN IC 审中-公开
标题翻译：具有这种IC的测试布置和测试方法的模拟IC
公开(公告)号：WO2007049210A2
公开(公告)日：2007-05-03
申请号：PCT/IB2006/053878
申请日：2006-10-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , ZJAJO, Amir , BERGVELD, Hendrik, J. , SCHUTTERT, Rodger, F. , PINEDA DE GYVEZ, Jose de Jesus
发明人： ZJAJO, Amir , BERGVELD, Hendrik, J. , SCHUTTERT, Rodger, F. , PINEDA DE GYVEZ, Jose de Jesus
CPC分类号： G01R31/3167 , G01R31/31721 , G01R31/318536 , G01R31/318575
摘要： An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor (70) may be present in the power supply to facilitate structural testing of the analog stages in isolation.
摘要翻译：集成电路（IC）包括多个模拟级（10a-c），每个模拟级与电源（20; 20a-c）导电耦合，并且通过信号路径彼此导电耦合 12）; 以及用于测试所述多个模拟级的测试装置，所述测试装置包括输入装置，例如耦合到来自所述多个模拟级的每个模拟级的信号路径输入的模拟总线（40），输出装置用于将测试结果传送到集成电路的输出的总线（50），用于选择性地禁用模拟级的IC的偏置基础设施中的多个开关（36）等开关装置，以及诸如移位寄存器 60），用于控制切换装置。因此，IC的模拟级可以隔离测试和调试，而不需要通过核心的信号路径中的开关。电流传感器（70）可以存在于电源中以便于隔离地对模拟级的结构测试。

4. 发明申请

WO2009144661A1 INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT CONTROL METHOD 审中-公开
标题翻译：集成电路和集成电路控制方法
公开(公告)号：WO2009144661A1
公开(公告)日：2009-12-03
申请号：PCT/IB2009/052198
申请日：2009-05-26
申请人： NXP B.V. , PINEDA DE GYVEZ, Jose de Jesus , MEIJER, Rinze Ida Mechtildis Peter , GROOT, Cas
发明人： PINEDA DE GYVEZ, Jose de Jesus , MEIJER, Rinze Ida Mechtildis Peter , GROOT, Cas
IPC分类号： H03K19/00 , G06F1/32 , G11C11/4074
CPC分类号： H03K19/0016 , G06F1/3203 , G11C5/143 , G11C5/144 , H03K19/0005
摘要： The present application discloses an integrated circuit comprising a circuit portion (100) coupled between first and second power supply lines (110; 120); a first switch (115, 135) coupled between the first power supply line (110, 120) and the circuit portion (100) for disconnecting the circuit portion from the first power supply line during an inactive mode of the circuit portion; and an arrangement (315, 335, 410) for, during said inactive mode, providing the circuit portion (100) with a fraction of its active mode power supply at least when averaged over said inactive mode to prevent the circuit portion voltage to drop below a threshold value. The present application further discloses a method for controlling such an integrated circuit.
摘要翻译：本申请公开了一种集成电路，其包括耦合在第一和第二电源线（110; 120）之间的电路部分（100）。耦合在所述第一电源线（110,120）和所述电路部分（100）之间的第一开关（115,135），用于在所述电路部分的非活动模式期间将所述电路部分与所述第一电源线断开; 以及在所述非活动模式期间，至少在所述非活动模式下平均时，为电路部分（100）提供其一部分有源模式电源的布置（315,335,410），以防止电路部分电压降至低于一个阈值。本申请还公开了一种用于控制这种集成电路的方法。

5. 发明申请

WO2009004535A2 STATIC MEMORY DEVICES 审中-公开
标题翻译：静态存储器件
公开(公告)号：WO2009004535A2
公开(公告)日：2009-01-08
申请号：PCT/IB2008/052544
申请日：2008-06-25
申请人： NXP B.V. , ELVIRA VILLAGRA, Luis , MEIJER, Rinze, I., M. , PINEDA DE GYVEZ, Jose, de Jesus
发明人： ELVIRA VILLAGRA, Luis , MEIJER, Rinze, I., M. , PINEDA DE GYVEZ, Jose, de Jesus
IPC分类号： G11C11/412 , G11C11/417
CPC分类号： G11C11/413 , H01L27/0207 , H01L27/105
摘要： A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve readingand writing performance. One of the n-wells and p-wells can be globally biased. Error reduction and/or correction can be performed.
摘要翻译：半导体存储器件包括用于构成多个存储单元元件（40）的n阱（22）和p阱（24）。 n阱（22）和p-5阱（24）可以被反向偏置，以提高读取和写入性能。 n井和对井之一可能是全球性的偏差。可以执行错误减少和/或校正。

6. 发明申请

WO2006056902A1 SRAM TEST METHOD AND SRAM TEST ARRANGEMENT TO DETECT WEAK CELLS 审中-公开
标题翻译： SRAM测试方法和SRAM测试安排以检测弱电池
公开(公告)号：WO2006056902A1
公开(公告)日：2006-06-01
申请号：PCT/IB2005/053677
申请日：2005-11-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PINEDA DE GYVEZ, Jose de Jesus , AZIMANE, Mohamed , PAVLOV, Andrei, S.
发明人： PINEDA DE GYVEZ, Jose de Jesus , AZIMANE, Mohamed , PAVLOV, Andrei, S.
IPC分类号： G11C29/50
CPC分类号： G11C29/50
摘要： A method and a test arrangement for testing an SRAM having a first cell and a second cell coupled between a pair of bitlines is disclosed. In a first step (410), a data value is stored in the first cell being the cell under test (CUT), and its complement is stored in a second cell, being the reference cell. Next, the bitlines are precharged to a predefined voltage (step 420). Subsequently, the wordline of the reference cell is enabled for a predefined time period (step 430), for instance by providing the wordline with a number of voltage pulses. This causes a drop in voltage of the bitline coupled to the logic '0' node of the reference cell. In a subsequent step (440), the wordline of the CUT is enabled, which exposes the CUT to the bitline with the reduced voltage. This is equivalent to weakly overwriting the CUT. Finally, the data value in the CUT is evaluated. If the data value has flipped, the CUT is a weak cell. Cells with varying levels of weakness can be detected by varying the reduced voltage on the aforementioned bitline.
摘要翻译：公开了一种用于测试具有耦合在一对位线之间的第一单元和第二单元的SRAM的方法和测试装置。在第一步骤（410）中，数据值存储在作为被测单元（CUT）的第一单元中，并且其补码存储在作为参考单元的第二单元中。接下来，将位线预充电到预定电压（步骤420）。随后，参考单元的字线被启用预定时间段（步骤430），例如通过为字线提供多个电压脉冲。这导致耦合到参考单元的逻辑“0”节点的位线的电压下降。在随后的步骤（440）中，CUT的字线被使能，其将CUT以降低的电压公开到位线。这相当于弱覆盖了CUT。最后，评估CUT中的数据值。如果数据值已翻转，则CUT是弱单元。可以通过改变上述位线上的降低的电压来检测具有不同弱度水平的细胞。

7. 发明申请

WO2008135917A1 IC TESTING METHODS AND APPARATUS 审中-公开
标题翻译： IC测试方法和设备
公开(公告)号：WO2008135917A1
公开(公告)日：2008-11-13
申请号：PCT/IB2008/051679
申请日：2008-04-30
申请人： NXP B.V. , ZJAJO, Amir , BARRAGAN ASIAN, Manuel Jose , PINEDA DE GYVEZ, Jose de Jesus
发明人： ZJAJO, Amir , BARRAGAN ASIAN, Manuel Jose , PINEDA DE GYVEZ, Jose de Jesus
IPC分类号： G01R31/3187
CPC分类号： G01R31/318558
摘要： An integrated circuit comprises a device under test and embedded test circuitry. The embedded test circuitry comprises a plurality of process monitoring sensors (14), a threshold circuit (22) for comparing the sensor signals with a threshold window having an upper and a lower limit and a digital interface (17) for outputting the threshold circuit signal. The process monitoring sensors (14) comprise circuitry based on the circuit elements of the device under test. This arrangement enables monitoring of circuit element performance, such as transistor properties, using process monitoring sensors which are embedded with the device under test, so that the same process parameter variations apply to the sensors as to the device under test. The sensors preferably match the physical layout of the device under test.
摘要翻译：集成电路包括被测器件和嵌入式测试电路。嵌入式测试电路包括多个过程监控传感器（14），用于将传感器信号与具有上限和下限的阈值窗口进行比较的阈值电路（22）和用于输出阈值电路信号的数字接口（17）。过程监控传感器（14）包括基于所测试设备的电路元件的电路。这种布置使得可以使用嵌入被测器件的过程监控传感器来监控诸如晶体管特性的电路元件性能，使得相同的工艺参数变化适用于被测器件的传感器。传感器优选地与待测设备的物理布局相匹配。

8. 发明申请

WO2007049210A3 ANALOG IC HAVING TEST ARRANGEMENT AND TEST METHOD FOR SUCH AN IC 审中-公开
标题翻译：具有这种IC的测试装置和测试方法的模拟IC
公开(公告)号：WO2007049210A3
公开(公告)日：2007-07-26
申请号：PCT/IB2006053878
申请日：2006-10-20
申请人： NXP BV , ZJAJO AMIR , BERGVELD HENDRIK J , SCHUTTERT RODGER F , PINEDA DE GYVEZ JOSE DE JESUS
发明人： ZJAJO AMIR , BERGVELD HENDRIK J , SCHUTTERT RODGER F , PINEDA DE GYVEZ JOSE DE JESUS
IPC分类号： G01R31/3185 , G01R31/317
CPC分类号： G01R31/3167 , G01R31/31721 , G01R31/318536 , G01R31/318575
摘要： An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor (70) may be present in the power supply to facilitate structural testing of the analog stages in isolation.
摘要翻译：一种集成电路（IC）包括多个模拟级（10A-C）中，每个模拟级被导电地耦合到电源（20; 20A-C），并通过一个信号路径被导电地耦合到彼此（ 12）; 以及用于测试所述多个模拟级的测试布置，测试装置包括输入装置，诸如耦合到从所述多个模拟级的每个模拟级的信号路径的输入的模拟总线（40），输出装置，如进一步模拟总线（50），用于测试结果传送到集成电路的输出，开关装置如在IC的有选择地禁止的模拟阶段偏置基础设施的多个开关（36），以及控制装置，这样的移位寄存器（ 60），用于控制开关装置。因此，IC的模拟级可以独立进行测试和调试，而不需要通过内核的信号路径中的开关。电流传感器（70）可以存在于电源中以便于隔离模拟级的结构测试。

9. 发明申请

WO2007080527A2 TESTABLE INTEGRATED CIRCUIT AND IC TEST METHOD 审中-公开
标题翻译：可测试的集成电路和IC测试方法
公开(公告)号：WO2007080527A2
公开(公告)日：2007-07-19
申请号：PCT/IB2007050036
申请日：2007-01-05
申请人： NXP BV , GOEL SANDEEPKUMAR , PINEDA DE GYVEZ JOSE DE JESUS , MEIJER RINZE I M P
发明人： GOEL SANDEEPKUMAR , PINEDA DE GYVEZ JOSE DE JESUS , MEIJER RINZE I M P
IPC分类号： G01R31/317 , G01R31/3185
CPC分类号： G01R31/31715 , G01R31/31723 , G01R31/318569 , G01R31/318572
摘要： An integrated circuit (200) comprises a functional block (130) conductively coupled to a supply rail (110) via one or more switches (115). The IC further comprises selection means (220) responsive to a test enable signal for activating the one or more switches (115) in a test mode of the IC and evaluation means such as a comparator (230) having a first input coupled to a reference signal source (215) and having a second input coupled to a node (225) between the one or more switches (115) and the functional block (130) for evaluating the behaviour of the one or more switches (115) based on the reference signal and a signal from the node (225). Thus, the present invention provides a design for testability solution for testing power switches.
摘要翻译：集成电路（200）包括经由一个或多个开关（115）导电耦合到电源轨（110）的功能块（130）。 IC还包括响应于在IC的测试模式下激活一个或多个开关（115）的测试使能信号的选择装置（220）和诸如比较器（230）的评估装置，该比较器具有耦合到参考的第一输入信号源（215）并且具有耦合到所述一个或多个开关（115）和所述功能块（130）之间的节点（225）的第二输入，用于基于所述参考来评估所述一个或多个开关（115）的行为信号和来自节点（225）的信号。因此，本发明提供了用于测试功率开关的可测试性解决方案的设计。

10. 发明申请

WO2010007585A3 LOW POWER IMAGE COMPRESSION 审中-公开
标题翻译：低功率图像压缩
公开(公告)号：WO2010007585A3
公开(公告)日：2011-01-06
申请号：PCT/IB2009053059
申请日：2009-07-15
申请人： NXP BV , PU YU , PINEDA DE GYVEZ JOSE DE JESUS
发明人： PU YU , PINEDA DE GYVEZ JOSE DE JESUS
IPC分类号： H04N7/26 , H04N7/30
CPC分类号： H04N19/436 , H04N19/12 , H04N19/156 , H04N19/42 , H04N19/60 , H04N19/65
摘要： A data processing apparatus for compressing image data is described comprising at least two circuits configured for generating a quantized discrete cosine transform of data of an image, and an encoder configured for entropy encoding the quantized discrete cosine transform of data of an image generated by one of the at least two circuits.
摘要翻译：描述了一种用于压缩图像数据的数据处理装置，包括被配置用于产生图像数据的量化离散余弦变换的至少两个电路，和被配置用于熵编码由以下之一生成的图像数据的量化离散余弦变换至少两个电路。

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