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1. 发明申请

WO2007127014A3 PROGRAMMING A NORMALLY SINGLE PHASE CHALCOGENIDE MATERIAL FOR USE AS A MEMORY OR FPLA 审中-公开
标题翻译：编程用作存储器或FPLA的正常单相氯化铝材料
公开(公告)号：WO2007127014A3
公开(公告)日：2008-06-26
申请号：PCT/US2007007859
申请日：2007-03-29
申请人： OVONYX INC , GORDON GEORGE A , PARKINSON WARD D , PETERS JOHN M , LOWREY TYLER A , OVSHINSKY STANFORD , WICKER GUY C , KARPOV ILYA V , KUO CHARLES C
发明人： GORDON GEORGE A , PARKINSON WARD D , PETERS JOHN M , LOWREY TYLER A , OVSHINSKY STANFORD , WICKER GUY C , KARPOV ILYA V , KUO CHARLES C
IPC分类号： H01L45/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2013/0092 , G11C2213/77 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200°C for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.
摘要翻译：可以使用稳定的硫属化物玻璃来实现记忆，其被定义为当暴露于200℃下30分钟或更少时不会改变为通常结晶相的通常为非晶态的硫族化物材料。可以通过改变材料的阈值电压来编程不同的状态。可以用不同幅度和/或不同脉冲下降时间的脉冲来改变阈值电压。可以使用两种不同状态的阈值电压之间的参考电平进行读取。通常不需要单独的访问设备。

2. 发明申请

WO1989011733A1 ALPHA SHIELDED TISI2 LOCAL INTERCONNECTS 审中-公开
公开(公告)号：WO1989011733A1
公开(公告)日：1989-11-30
申请号：PCT/US1988001760
申请日：1988-05-24
申请人： MICRON TECHNOLOGY, INC. , TONG, Paul, Chak, Foon , LOWREY, Tyler, A. , PARKINSON, Ward, D.
发明人： MICRON TECHNOLOGY, INC.
IPC分类号： H01L21/283
CPC分类号： H01L21/76895 , H01L21/28518 , H01L21/76879
摘要： Low resistivity interconnects and silicided N+/P+ active area are formed by sputtering a blanket layer of titanium (33) onto a wafer surface (13) which has the interconnection pattern defined by a thin polysilicon layer (29). A thin oxide layer (27) underneath the polysilicon interconnection pattern serves as an etch stop in the local interconnect photo/etch step. This unprotected oxide layer remaining on top of the N+/P+ active area will be removed by a wet etch prior to the sputtering step. Titanium is then reacted with the polysilicon to form TiSi2, and unreacted titanium and TiN are removed. A subsequent metallization layer acts as an alpha radiation shield and as a capacitive ground.
摘要翻译：通过将钛（33）的覆盖层溅射到由薄多晶硅层（29）限定的互连图案的晶片表面（13）上形成低电阻率互连和硅化N + / P +有源区。在多晶硅互连图案下方的薄氧化物层（27）用作局部互连光刻/蚀刻步骤中的蚀刻停止。残留在N + / P +有效面积顶部的未保护的氧化物层将在溅射步骤之前通过湿式蚀刻去除。然后使钛与多晶硅反应形成TiSi 2，并除去未反应的钛和TiN。随后的金属化层用作α辐射屏蔽和作为电容地。

3. 发明申请

WO2007075392A1 WRITING PHASE CHANGE MEMORIES 审中-公开
标题翻译：书写相变记忆
公开(公告)号：WO2007075392A1
公开(公告)日：2007-07-05
申请号：PCT/US2006/047868
申请日：2006-12-15
申请人： OVONYX, INC. , PARKINSON, Ward, D.
发明人： PARKINSON, Ward, D.
IPC分类号： G11C16/02
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0097 , G11C2013/0078 , G11C2013/0092
摘要： In accordance with some embodiments, the endurance of phase change memory cells may be increased. This increase may be accomplished with adequate margin by reducing the current used to write the reset state. Generally, that current will be a current less than the saturated current.
摘要翻译：根据一些实施例，可以增加相变存储器单元的耐久性。这种增加可以通过减少用于写入复位状态的电流以足够的余量来实现。通常，该电流将是小于饱和电流的电流。

4. 发明申请

WO2007127014A2 PROGRAMMING A NORMALLY SINGLE PHASE CHALCOGENIDE MATERIAL FOR USE AS A MEMORY OR FPLA 审中-公开
标题翻译：编程用作存储器或FPLA的正常单相氯化铝材料
公开(公告)号：WO2007127014A2
公开(公告)日：2007-11-08
申请号：PCT/US2007/007859
申请日：2007-03-29
申请人： OVONYX, INC. , GORDON, George, A. , PARKINSON, Ward, D. , PETERS, John, M. , LOWREY, Tyler, A. , OVSHINSKY, Stanford , WICKER, Guy, C. , KARPOV, Ilya, V. , KUO, Charles, C.
发明人： GORDON, George, A. , PARKINSON, Ward, D. , PETERS, John, M. , LOWREY, Tyler, A. , OVSHINSKY, Stanford , WICKER, Guy, C. , KARPOV, Ilya, V. , KUO, Charles, C.
IPC分类号： H01L45/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2013/0092 , G11C2213/77 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200°C for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.
摘要翻译：可以用稳定的硫族化物玻璃来实现记忆，其被定义为当暴露于200℃下30分钟或更少时不会改变为通常结晶相的通常为非晶态的硫族化物材料。可以通过改变材料的阈值电压来编程不同的状态。可以用不同幅度和/或不同脉冲下降时间的脉冲来改变阈值电压。可以使用两种不同状态的阈值电压之间的参考电平进行读取。通常不需要单独的访问设备。

5. 发明申请

WO1989011732A1 TISI2 LOCAL INTERCONNECTS 审中-公开
标题翻译： TISI2本地互联
公开(公告)号：WO1989011732A1
公开(公告)日：1989-11-30
申请号：PCT/US1988001759
申请日：1988-05-24
申请人： MICRON TECHNOLOGY, INC. , TONG, Paul, Chak, Foon , LOWREY, Tyler, A. , PARKINSON, Ward, D.
发明人： MICRON TECHNOLOGY, INC.
IPC分类号： H01L21/283
CPC分类号： H01L21/76879 , H01L21/28518 , H01L21/76895
摘要： Low resistivity interconnects and silicided N+/P+ active area are formed by sputtering a blanket layer of titanium (33) onto a wafer (13) surface which has the interconnection pattern defined by a thin polysilicon layer (29). A thin oxide layer (27) underneath the polysilicon (29) interconnection pattern serves as an etch stop in the local interconnect photo/etch step. This unprotected oxide layer remaining on top of the N+/P+ active area will be removed by a wet etch prior to the sputtering step. Titanium is then sintered, resulting in conversion of titanium to TiSi2 and TiN. Unreacted titanium and TiN are removed and the remaining TiSi2 provides silicided N+/P+ junctions and a low resistance interconnect level. Advantages of the invention include a low resistance self-aligned contact procedure for the bitline formation, and elimination of the minimal spacing requirement between access transistors imposed by the traditional non self-aligned contact approach.
摘要翻译：通过将钛（33）的覆盖层溅射到具有由多晶硅薄层（29）限定的互连图案的晶片（13）表面上而形成低电阻率互连和硅化N + / P +有源区。在多晶硅（29）互连图案下方的薄氧化物层（27）用作局部互连光刻/蚀刻步骤中的蚀刻停止。残留在N + / P +有效面积顶部的未保护的氧化物层将在溅射步骤之前通过湿式蚀刻去除。然后将钛烧结，导致钛转化为TiSi 2和TiN。去除未反应的钛和TiN，剩余的TiSi 2提供硅化N + / P +结和低电阻互连水平。本发明的优点包括用于位线形成的低电阻自对准接触程序，以及消除由传统的非自对准接触方法施加的存取晶体管之间的最小间隔要求。

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