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1. 发明申请

WO2010059872A3 FM TRANSMITTER AND NON-FM RECEIVER INTEGRATED ON SINGLE CHIP 审中-公开
公开(公告)号：WO2010059872A3
公开(公告)日：2010-05-27
申请号：PCT/US2009/065213
申请日：2009-11-19
申请人： QUALCOMM INCORPORATED , LIN, I-Hsiang , PAN, Tzu-Wang , ZENG, Yi
发明人： LIN, I-Hsiang , PAN, Tzu-Wang , ZENG, Yi
IPC分类号： H04B1/52
摘要： Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

2. 发明申请

WO2013023188A3 CLOCK SHARING BETWEEN CORES ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在集成电路之间的时钟共享
公开(公告)号：WO2013023188A3
公开(公告)日：2013-07-18
申请号：PCT/US2012050466
申请日：2012-08-10
申请人： QUALCOMM INC , KIM BEOMSUP , PAN TZU-WANG , KIM YOUNG GON
发明人： KIM BEOMSUP , PAN TZU-WANG , KIM YOUNG GON
IPC分类号： G06F1/10 , H03L7/181 , H04B1/40
CPC分类号： H03L7/0995 , H03L7/1976 , H04B1/403
摘要： An integrated circuit is described. The integrated circuit includes a global positioning system core that generates a GPS clock signal using an inductor-capacitor voltage controlled oscillator. The integrated circuit also includes a transceiver core configured to use the GPS clock signal. The transceiver core may not include a voltage controlled oscillator.
摘要翻译：描述了集成电路。集成电路包括使用电感器电容器压控振荡器产生GPS时钟信号的全球定位系统核心。集成电路还包括被配置为使用GPS时钟信号的收发机芯。收发机芯可能不包括压控振荡器。

3. 发明申请

WO2013023188A2 CLOCK SHARING BETWEEN CORES ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：时钟在集成电路上的核心之间共享
公开(公告)号：WO2013023188A2
公开(公告)日：2013-02-14
申请号：PCT/US2012/050466
申请日：2012-08-10
申请人： QUALCOMM INCORPORATED , KIM, Beomsup , PAN, Tzu-wang , KIM, Young Gon
发明人： KIM, Beomsup , PAN, Tzu-wang , KIM, Young Gon
IPC分类号： H04B1/40
CPC分类号： H03L7/0995 , H03L7/1976 , H04B1/403
摘要： An integrated circuit is described. The integrated circuit includes a global positioning system core that generates a GPS clock signal using an inductor-capacitor voltage controlled oscillator. The integrated circuit also includes a transceiver core configured to use the GPS clock signal. The transceiver core may not include a voltage controlled oscillator.
摘要翻译：描述集成电路。该集成电路包括一个全球定位系统内核，该内核使用电感电容压控振荡器产生GPS时钟信号。集成电路还包括被配置为使用GPS时钟信号的收发器核心。收发器内核可能不包含压控振荡器。

4. 发明申请

WO2011060322A1 ACTIVE ANALOG FILTER HAVING A MOS CAPACITOR DEVICE WITH IMPROVED LINEARITY 审中-公开
标题翻译：具有改善线性的MOS电容器的主动模拟滤波器
公开(公告)号：WO2011060322A1
公开(公告)日：2011-05-19
申请号：PCT/US2010/056615
申请日：2010-11-12
申请人： QUALCOMM Incorporated , PARK, Sunghyun , LI, Xiaoyong , PAN, Tzu-wang
发明人： PARK, Sunghyun , LI, Xiaoyong , PAN, Tzu-wang
IPC分类号： H03H11/12
CPC分类号： H03H11/126
摘要： An active analog filter (700, 1000) having a MOS capacitor device (730, 1030) with improved linearity is proposed. In an exemplary embodiment, dc bias voltage sources (755, 745) alter the capacitance of MOS varactors (740, 750) connected in anti parallel so that the total capacitance of the MOS capacitor device remains constant or within a range over the voltage range of the filter and the filter linearity is set. In a further exemplary embodiment the output stage (1070) of the operational amplifier circuit (1020) of the active analog filter (1000) is modified so that the dc bias voltage is provided by resistors (1055, 1045) connected to a current source (1060) already existing in the filter. Thus the linearity is set and the die area is significantly reduced.
摘要翻译：提出了一种具有提高线性度的MOS电容器件（730,1030）的有源模拟滤波器（700,1000）。在示例性实施例中，直流偏置电压源（755,745）改变以反并联方式连接的MOS可变电抗器（740,750）的电容，使得MOS电容器装置的总电容保持恒定或超过电压范围滤波器和滤波器线性度被设置。在另一示例性实施例中，有源模拟滤波器（1000）的运算放大器电路（1020）的输出级（1070）被修改，使得直流偏置电压由连接到电流源的电阻（1055,1045） 1060）已经存在于过滤器中。因此，设置线性度并且模具面积显着减小。

5. 发明申请

WO2010129925A3 OVERLAPPING, TWO-SEGMENT CAPACITOR BANK FOR VCO FREQUENCY TUNING 审中-公开
标题翻译：用于VCO频率调谐的重叠，双段电容器库
公开(公告)号：WO2010129925A3
公开(公告)日：2010-11-11
申请号：PCT/US2010/034129
申请日：2010-05-07
申请人： QUALCOMM Incorporated , ZENG, Yi , PAN, Tzu-Wang , LIN, I-Hsiang
发明人： ZENG, Yi , PAN, Tzu-Wang , LIN, I-Hsiang
IPC分类号： H03B5/12
摘要： A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.
摘要翻译： VCO（例如，在FM接收器中）包括LC谐振回路。 LC谐振回路包括一个粗调电容器组和一个精调电容器组。粗调电容器组包含多个数字控制的粗调电容器元件，每个电容器元件在激活时提供第一电容值。微调电容器组包含多个数字控制微调电容器元件，每个电容器元件在激活时提供第二电容值。为了解决电容器失配的实际问题，通过选择第一和第二电容值产生整个VCO调谐范围内的电容重叠，使得精细电容器组的电容值大于第一电容值，当所有的数字控制精细微调电容器组的电容元件是有效的。

6. 发明申请

WO2010126844A1 JAMMER DETECTION BASED ADAPTIVE PLL BANDWIDTH ADJUSTMENT IN FM RECEIVER 审中-公开
标题翻译：基于JAMMER检测的FM接收器中的自适应PLL带宽调整
公开(公告)号：WO2010126844A1
公开(公告)日：2010-11-04
申请号：PCT/US2010/032455
申请日：2010-04-26
申请人： QUALCOMM Incorporated , ZENG, Yi , PAN, Tzu-wang , LIN, I-Hsiang , DUNWORTH, Jeremy , TRIKHA, Pushp , APTE, Rahul
发明人： ZENG, Yi , PAN, Tzu-wang , LIN, I-Hsiang , DUNWORTH, Jeremy , TRIKHA, Pushp , APTE, Rahul
IPC分类号： H04B1/10 , H03L7/107
CPC分类号： H04B1/1027
摘要： A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.
摘要翻译： FM接收机内的频率合成器采用锁相环（PLL）来产生本地振荡器（LO）信号。 LO信号提供给混频器。 FM接收机还包括干扰检测功能。如果没有检测到干扰，则PLL的环路带宽被设置为具有相对较高的值，从而有利于抑制带内剩余FM。如果检测到干扰，则将PLL的环路带宽设置为具有相对较低的值，从而有利于抑制带外SSB相位噪声。通过根据是否检测到干扰信号来自适应地改变环路带宽，可以放宽PLL内的子电路的性能要求，同时仍然满足带内剩余FM和带外SSB相位噪声要求。通过允许PLL的VCO由于环路带宽的自适应变化而产生更多的相位噪声，可以降低VCO的功耗。

7. 发明申请

WO2010059872A2 FM TRANSMITTER AND NON-FM RECEIVER INTEGRATED ON SINGLE CHIP 审中-公开
标题翻译： FM发射机和非FM收音机集成在单芯片上
公开(公告)号：WO2010059872A2
公开(公告)日：2010-05-27
申请号：PCT/US2009065213
申请日：2009-11-19
申请人： QUALCOMM INC , LIN I-HSIANG , PAN TZU-WANG , ZENG YI
发明人： LIN I-HSIANG , PAN TZU-WANG , ZENG YI
IPC分类号： H03D5/00
CPC分类号： H04B1/525
摘要： Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.
摘要翻译：示例性实施例包括可以在同一IC芯片上实现的调频（FM）发射机和非FM接收机。 FM发射机可以包括数字FM调制器，低通滤波器，放大器和LC电路。数字FM调制器可以接收数字输入信号，使用数字输入信号执行FM调制，并提供数字FM信号。低通滤波器可以对数字FM信号进行滤波并提供滤波后的FM信号。放大器可以放大经滤波的FM信号并提供输出FM信号。 LC振荡电路可以对输出的FM信号进行滤波。数字FM调制器可以通过改变PLL内的多模式分频器的可变分频比来执行FM调制。 Δ-Σ调制器可以接收数字输入信号并产生用于获得可变分频比的调制器输出信号。

8. 发明申请

WO2010151890A1 FM TRANSMITTER WITH A DELTA-SIGMA MODULATOR AND A PHASE-LOCKED LOOP 审中-公开
标题翻译：具有三角形调制器和相位锁定环的FM发射器
公开(公告)号：WO2010151890A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/040247
申请日：2010-06-28
申请人： QUALCOMM Incorporated , TRIKHA, Pushp K. , PAN, Tzu-wang , YANG, Eugene , ZENG, Yi , LIN, I-Hsiang , VISHWANATH, Tg
发明人： TRIKHA, Pushp K. , PAN, Tzu-wang , YANG, Eugene , ZENG, Yi , LIN, I-Hsiang , VISHWANATH, Tg
IPC分类号： H04H20/57 , H04B1/40 , H04H40/45
CPC分类号： H04H20/57 , H04H40/45
摘要： A frequency modulation (FM) transmitter implemented with a delta-sigma modulator and a phase-locked loop (PLL) is described. The delta-sigma modulator receives a modulating signal (e.g., an FM stereo multiplex (MPX) signal) and provides a modulator output signal. The PLL performs frequency modulation based on the modulator output signal and provides an FM signal. The FM transmitter may further include a gain/phase compensation unit and a scaling unit. The compensation unit may compensate the modulating signal for the closed-loop response of the PLL. The scaling unit may scale the amplitude of the modulating signal based on a gain to obtain a target frequency deviation for the FM signal. The PLL may operate in a transmit mode or a receive mode, may perform frequency modulation in the transmit mode, and may provide a local oscillator (LO) signal at a fixed frequency in the receive mode.
摘要翻译：描述了用Δ-Σ调制器和锁相环（PLL）实现的频率调制（FM）发射机。 Δ-Σ调制器接收调制信号（例如，FM立体声多路复用（MPX）信号），并提供调制器输出信号。 PLL根据调制器输出信号进行调频，并提供FM信号。 FM发射机还可以包括增益/相位补偿单元和缩放单元。补偿单元可以补偿PLL的闭环响应的调制信号。缩放单元可以基于增益来调整调制信号的幅度，以获得FM信号的目标频率偏差。 PLL可以以发送模式或接收模式工作，可以在发送模式下执行频率调制，并且可以在接收模式下以固定频率提供本地振荡器（LO）信号。

9. 发明申请

WO2010048232A1 TUNABLE FILTERS WITH LOWER RESIDUAL SIDEBAND 审中-公开
标题翻译：具有较低残留边的TUNABLE过滤器
公开(公告)号：WO2010048232A1
公开(公告)日：2010-04-29
申请号：PCT/US2009/061385
申请日：2009-10-20
申请人： QUALCOMM INCORPORATED , WANG, Cheng-Han , BROCKENBROUGH, Roger , PAN, Tzu-wang
发明人： WANG, Cheng-Han , BROCKENBROUGH, Roger , PAN, Tzu-wang
IPC分类号： H03H11/12 , H03F3/45 , H04B1/10
CPC分类号： H03H11/1291
摘要： An apparatus includes first (220a) and second (220b) filters and a bandwidth control circuit (270). The first filter (220a) operates as part of a first oscillator in a first mode and filters a first input signal and provides a first output signal in a second mode. The second filter (220b) operates as part of a second oscillator in the first mode and filters a second input signal and provides a second output signal in the second mode. The bandwidth control circuit (270) adjusts the bandwidth of the first and second filters (220a, 220b) in the first mode, e.g., adjusts the oscillation frequency of each oscillator to obtain a target bandwidth for an associated filter. The apparatus may further include first and second gain control circuits (250a, 250b). Each gain control circuit (250a, 250b) may vary the amplitude of an oscillator signal from an associated oscillator and/or set a gain of an associated filter in the first mode.
摘要翻译：一种装置包括第一（220a）和第二（220b）滤波器和带宽控制电路（270）。第一滤波器（220a）在第一模式中作为第一振荡器的一部分进行操作，并且对第一输入信号进行滤波并在第二模式中提供第一输出信号。第二滤波器（220b）在第一模式中作为第二振荡器的一部分工作，并且对第二输入信号进行滤波并在第二模式中提供第二输出信号。带宽控制电路（270）在第一模式中调整第一和第二滤波器（220a，220b）的带宽，例如调整每个振荡器的振荡频率以获得相关滤波器的目标带宽。该装置还可以包括第一和第二增益控制电路（250a，250b）。每个增益控制电路（250a，250b）可以改变来自相关振荡器的振荡器信号的幅度和/或在第一模式中设置相关联的滤波器的增益。

10. 发明申请

WO2010129925A2 OVERLAPPING, TWO-SEGMENT CAPACITOR BANK FOR VCO FREQUENCY TUNING 审中-公开
标题翻译：用于VCO频率调谐的两部分电容器
公开(公告)号：WO2010129925A2
公开(公告)日：2010-11-11
申请号：PCT/US2010034129
申请日：2010-05-07
申请人： QUALCOMM INC , ZENG YI , PAN TZU-WANG , LIN I-HSIANG
发明人： ZENG YI , PAN TZU-WANG , LIN I-HSIANG
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1253 , H03B5/1265 , H03B5/1293
摘要： A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.
摘要翻译： VCO（例如，在FM接收机中）包括LC谐振回路。 LC谐振槽包括一个粗调谐电容器组和一个微调电容器组。粗调谐电容器组包含多个数字控制的粗调电容器元件，每个主调制电容器元件在有源时提供第一电容值。微调电容器组包含多个数字控制的微调电容器元件，每个微调电容器元件在有源时提供第二电容值。为了解决电容器失配的实际问题，通过选择第一和第二电容值来创建整个VCO调谐范围内的电容重叠，使得当全部数字控制的精细时，精细电容器组的电容值大于第一电容值精细电容器组的调谐电容器元件是有效的。

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