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1. 发明申请

WO2012178141A1 SYSTEMATIC INTERMODULATION DISTORTION CALIBRATION FOR A DIFFERENTIAL LNA 审中-公开
标题翻译：差分LNA的系统互变异常校准
公开(公告)号：WO2012178141A1
公开(公告)日：2012-12-27
申请号：PCT/US2012/043918
申请日：2012-06-24
申请人： QUALCOMM Incorporated , WANG, Cheng-Han , ZHAO, Liang , KIM, Hong Sun , LIN, I-Hsiang
发明人： WANG, Cheng-Han , ZHAO, Liang , KIM, Hong Sun , LIN, I-Hsiang
IPC分类号： H03F3/189 , H04B1/10
CPC分类号： H03F3/193 , H03F1/3211 , H03F3/45188 , H03F2203/45386 , H04B1/1036
摘要： Systematic IM2 calibration for a differential LNA is disclosed. In an aspect, an apparatus includes an amplifier configured to output an amplified signal having a level of systematic pre-mixer IM2 distortion, a detector configured to detect the level of the systematic pre-mixer IM2 distortion in the amplified signal, and a bias signal generator configured to generate at least one bias signal configured to adjust the amplifier to reduce the level of the systematic pre-mixer IM2 distortion.
摘要翻译：公开了用于差分LNA的系统IM2校准。一方面，一种装置包括：放大器，被配置为输出具有系统预混频器IM2失真电平的放大信号;检测器，被配置为检测放大信号中的系统预混频器IM2失真的电平;以及偏置信号配置成产生至少一个偏置信号的发生器，所述至少一个偏置信号被配置为调节放大器以减小系统预混频器IM2失真的电平。

2. 发明申请

WO2010129925A2 OVERLAPPING, TWO-SEGMENT CAPACITOR BANK FOR VCO FREQUENCY TUNING 审中-公开
标题翻译：用于VCO频率调谐的两部分电容器
公开(公告)号：WO2010129925A2
公开(公告)日：2010-11-11
申请号：PCT/US2010034129
申请日：2010-05-07
申请人： QUALCOMM INC , ZENG YI , PAN TZU-WANG , LIN I-HSIANG
发明人： ZENG YI , PAN TZU-WANG , LIN I-HSIANG
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1253 , H03B5/1265 , H03B5/1293
摘要： A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.
摘要翻译： VCO（例如，在FM接收机中）包括LC谐振回路。 LC谐振槽包括一个粗调谐电容器组和一个微调电容器组。粗调谐电容器组包含多个数字控制的粗调电容器元件，每个主调制电容器元件在有源时提供第一电容值。微调电容器组包含多个数字控制的微调电容器元件，每个微调电容器元件在有源时提供第二电容值。为了解决电容器失配的实际问题，通过选择第一和第二电容值来创建整个VCO调谐范围内的电容重叠，使得当全部数字控制的精细时，精细电容器组的电容值大于第一电容值精细电容器组的调谐电容器元件是有效的。

3. 发明申请

WO2010129925A3 OVERLAPPING, TWO-SEGMENT CAPACITOR BANK FOR VCO FREQUENCY TUNING 审中-公开
标题翻译：用于VCO频率调谐的重叠，双段电容器库
公开(公告)号：WO2010129925A3
公开(公告)日：2010-11-11
申请号：PCT/US2010/034129
申请日：2010-05-07
申请人： QUALCOMM Incorporated , ZENG, Yi , PAN, Tzu-Wang , LIN, I-Hsiang
发明人： ZENG, Yi , PAN, Tzu-Wang , LIN, I-Hsiang
IPC分类号： H03B5/12
摘要： A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.
摘要翻译： VCO（例如，在FM接收器中）包括LC谐振回路。 LC谐振回路包括一个粗调电容器组和一个精调电容器组。粗调电容器组包含多个数字控制的粗调电容器元件，每个电容器元件在激活时提供第一电容值。微调电容器组包含多个数字控制微调电容器元件，每个电容器元件在激活时提供第二电容值。为了解决电容器失配的实际问题，通过选择第一和第二电容值产生整个VCO调谐范围内的电容重叠，使得精细电容器组的电容值大于第一电容值，当所有的数字控制精细微调电容器组的电容元件是有效的。

4. 发明申请

WO2010126844A1 JAMMER DETECTION BASED ADAPTIVE PLL BANDWIDTH ADJUSTMENT IN FM RECEIVER 审中-公开
标题翻译：基于JAMMER检测的FM接收器中的自适应PLL带宽调整
公开(公告)号：WO2010126844A1
公开(公告)日：2010-11-04
申请号：PCT/US2010/032455
申请日：2010-04-26
申请人： QUALCOMM Incorporated , ZENG, Yi , PAN, Tzu-wang , LIN, I-Hsiang , DUNWORTH, Jeremy , TRIKHA, Pushp , APTE, Rahul
发明人： ZENG, Yi , PAN, Tzu-wang , LIN, I-Hsiang , DUNWORTH, Jeremy , TRIKHA, Pushp , APTE, Rahul
IPC分类号： H04B1/10 , H03L7/107
CPC分类号： H04B1/1027
摘要： A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.
摘要翻译： FM接收机内的频率合成器采用锁相环（PLL）来产生本地振荡器（LO）信号。 LO信号提供给混频器。 FM接收机还包括干扰检测功能。如果没有检测到干扰，则PLL的环路带宽被设置为具有相对较高的值，从而有利于抑制带内剩余FM。如果检测到干扰，则将PLL的环路带宽设置为具有相对较低的值，从而有利于抑制带外SSB相位噪声。通过根据是否检测到干扰信号来自适应地改变环路带宽，可以放宽PLL内的子电路的性能要求，同时仍然满足带内剩余FM和带外SSB相位噪声要求。通过允许PLL的VCO由于环路带宽的自适应变化而产生更多的相位噪声，可以降低VCO的功耗。

5. 发明申请

WO2010059872A2 FM TRANSMITTER AND NON-FM RECEIVER INTEGRATED ON SINGLE CHIP 审中-公开
标题翻译： FM发射机和非FM收音机集成在单芯片上
公开(公告)号：WO2010059872A2
公开(公告)日：2010-05-27
申请号：PCT/US2009065213
申请日：2009-11-19
申请人： QUALCOMM INC , LIN I-HSIANG , PAN TZU-WANG , ZENG YI
发明人： LIN I-HSIANG , PAN TZU-WANG , ZENG YI
IPC分类号： H03D5/00
CPC分类号： H04B1/525
摘要： Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.
摘要翻译：示例性实施例包括可以在同一IC芯片上实现的调频（FM）发射机和非FM接收机。 FM发射机可以包括数字FM调制器，低通滤波器，放大器和LC电路。数字FM调制器可以接收数字输入信号，使用数字输入信号执行FM调制，并提供数字FM信号。低通滤波器可以对数字FM信号进行滤波并提供滤波后的FM信号。放大器可以放大经滤波的FM信号并提供输出FM信号。 LC振荡电路可以对输出的FM信号进行滤波。数字FM调制器可以通过改变PLL内的多模式分频器的可变分频比来执行FM调制。 Δ-Σ调制器可以接收数字输入信号并产生用于获得可变分频比的调制器输出信号。

6. 发明申请

WO2013003818A1 GLOBAL NAVIGATION SATELLITE SYSTEM RECEIVER WITH FILTER BYPASS MODE FOR IMPROVED SENSITIVITY 审中-公开
标题翻译：全球导航卫星系统接收器，带有过滤器旁路模式，提高灵敏度
公开(公告)号：WO2013003818A1
公开(公告)日：2013-01-03
申请号：PCT/US2012/045126
申请日：2012-06-29
申请人： QUALCOMM Incorporated , GUDEM, Prasad Srinivasa Siva , ZHAO, Liang , LIN, I-Hsiang , XIONG, Zhijie , ASURI, Bhushan Shanti , HADJICHRISTOS, Aristotele
发明人： GUDEM, Prasad Srinivasa Siva , ZHAO, Liang , LIN, I-Hsiang , XIONG, Zhijie , ASURI, Bhushan Shanti , HADJICHRISTOS, Aristotele
IPC分类号： H04B1/38 , H04B1/52
CPC分类号： H04B1/525 , H04B1/3805
摘要： A global navigation satellite system receiver with filter bypass mode for improved sensitivity is disclosed. In an aspect, an apparatus is provided that includes a non-bypass signal path coupled to a receiver, the non-bypass signal path comprising a filter. The apparatus also includes a bypass signal path coupled to the receiver, the bypass signal path configure to bypass the filter, and a switch to couple an antenna to the non-bypass signal path during time intervals when signals transmitted by an unrelated local transmitter are transmitted with a signal power that exceeds a selected threshold, and to couple the antenna to the bypass signal path during other time intervals.
摘要翻译：公开了一种具有滤波器旁路模式以提高灵敏度的全球导航卫星系统接收机。在一方面，提供一种装置，其包括耦合到接收器的非旁路信号路径，非旁路信号路径包括滤波器。该装置还包括耦合到接收器的旁路信号路径，配置为旁路滤波器的旁路信号路径以及在由不相关的本地发射机发送的信号被发送的时间间隔期间将天线耦合到非旁路信号路径的开关信号功率超过所选阈值，并且在其它时间间隔期间将天线耦合到旁路信号路径。

7. 发明申请

WO2012050864A1 REDUCING NON-LINEARITIES IN A DIFFERENTIAL RECEIVER PATH PRIOR TO A MIXER USING CALIBRATION 审中-公开
标题翻译：使用校准减少混合器中差分接收器路径中的非线性
公开(公告)号：WO2012050864A1
公开(公告)日：2012-04-19
申请号：PCT/US2011/053612
申请日：2011-09-28
申请人： QUALCOMM Incorporated , AHRARI, Bahman , LIN, I-Hsiang
发明人： AHRARI, Bahman , LIN, I-Hsiang
IPC分类号： H04B1/10 , H03F1/32 , H04B17/00
CPC分类号： H04B1/109 , H03F1/3211 , H03F3/45188 , H03F2200/294 , H03F2203/45048 , H03F2203/45112 , H03F2203/45386
摘要： A receiver for a wireless device is described. The receiver includes a low noise amplifier that includes differential inputs. The receiver also includes a mixer coupled to the low noise amplifier. The receiver further includes second-order intermodulation reduction circuitry coupled to a stage subsequent to the low noise amplifier. The second-order intermodulation reduction circuitry provides a biasing of the differential inputs.
摘要翻译：描述了用于无线设备的接收机。接收机包括一个包含差分输入的低噪声放大器。接收机还包括耦合到低噪声放大器的混频器。接收机还包括耦合到低噪声放大器之后的级的二阶互调减少电路。二阶互调减少电路提供差分输入的偏置。

8. 发明申请

WO2010042763A1 CLOCK CLEAN-UP PHASE-LOCKED LOOP (PLL) 审中-公开
标题翻译：时钟清除锁相环（PLL）
公开(公告)号：WO2010042763A1
公开(公告)日：2010-04-15
申请号：PCT/US2009/060062
申请日：2009-10-08
申请人： QUALCOMM INCORPORATED , LIN, I-Hsiang , BROCKENBROUGH, Roger
发明人： LIN, I-Hsiang , BROCKENBROUGH, Roger
IPC分类号： H03L7/22 , H04B1/00
CPC分类号： H03L7/07 , H03L7/081 , H03L7/0995 , H03L7/197 , H03L7/22 , H03L7/23 , H04B1/0039
摘要： A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a first clock signal generated with a fractional divider ratio and having spurs due to abrupt frequency jumps. The first clock signal may be generated by a fractional-N frequency synthesizer external to the integrated circuit. The PLL generates a second clock signal with an integer divider ratio and having reduced spurs. The ADC digitizes an analog baseband signal based on the second clock signal and provides digital samples. The integrated circuit may further include a low noise amplifier (LNA), which may observe less spurs coupled via the substrate of the integrated circuit due to the use of the PLL to clean up the first clock signal.
摘要翻译：描述了可以减少杂散并提高接收机性能的时钟清理锁相环（PLL）。在一个示例性设计中，集成电路包括PLL和模数转换器（ADC）。 PLL接收以分数除数比产生的第一个时钟信号，并且由于突然的跳频而产生杂散。第一时钟信号可以由集成电路外部的分数N频率合成器产生。 PLL产生具有整数分频比的第二个时钟信号，并具有减少的杂散。 ADC根据第二个时钟信号数字化模拟基带信号，并提供数字采样。集成电路还可以包括低噪声放大器（LNA），由于使用PLL来清理第一时钟信号，可以观察到较小的经由集成电路的衬底耦合的杂散。

9. 发明申请

WO2010151890A1 FM TRANSMITTER WITH A DELTA-SIGMA MODULATOR AND A PHASE-LOCKED LOOP 审中-公开
标题翻译：具有三角形调制器和相位锁定环的FM发射器
公开(公告)号：WO2010151890A1
公开(公告)日：2010-12-29
申请号：PCT/US2010/040247
申请日：2010-06-28
申请人： QUALCOMM Incorporated , TRIKHA, Pushp K. , PAN, Tzu-wang , YANG, Eugene , ZENG, Yi , LIN, I-Hsiang , VISHWANATH, Tg
发明人： TRIKHA, Pushp K. , PAN, Tzu-wang , YANG, Eugene , ZENG, Yi , LIN, I-Hsiang , VISHWANATH, Tg
IPC分类号： H04H20/57 , H04B1/40 , H04H40/45
CPC分类号： H04H20/57 , H04H40/45
摘要： A frequency modulation (FM) transmitter implemented with a delta-sigma modulator and a phase-locked loop (PLL) is described. The delta-sigma modulator receives a modulating signal (e.g., an FM stereo multiplex (MPX) signal) and provides a modulator output signal. The PLL performs frequency modulation based on the modulator output signal and provides an FM signal. The FM transmitter may further include a gain/phase compensation unit and a scaling unit. The compensation unit may compensate the modulating signal for the closed-loop response of the PLL. The scaling unit may scale the amplitude of the modulating signal based on a gain to obtain a target frequency deviation for the FM signal. The PLL may operate in a transmit mode or a receive mode, may perform frequency modulation in the transmit mode, and may provide a local oscillator (LO) signal at a fixed frequency in the receive mode.
摘要翻译：描述了用Δ-Σ调制器和锁相环（PLL）实现的频率调制（FM）发射机。 Δ-Σ调制器接收调制信号（例如，FM立体声多路复用（MPX）信号），并提供调制器输出信号。 PLL根据调制器输出信号进行调频，并提供FM信号。 FM发射机还可以包括增益/相位补偿单元和缩放单元。补偿单元可以补偿PLL的闭环响应的调制信号。缩放单元可以基于增益来调整调制信号的幅度，以获得FM信号的目标频率偏差。 PLL可以以发送模式或接收模式工作，可以在发送模式下执行频率调制，并且可以在接收模式下以固定频率提供本地振荡器（LO）信号。

10. 发明申请

WO2010059872A3 FM TRANSMITTER AND NON-FM RECEIVER INTEGRATED ON SINGLE CHIP 审中-公开
公开(公告)号：WO2010059872A3
公开(公告)日：2010-05-27
申请号：PCT/US2009/065213
申请日：2009-11-19
申请人： QUALCOMM INCORPORATED , LIN, I-Hsiang , PAN, Tzu-Wang , ZENG, Yi
发明人： LIN, I-Hsiang , PAN, Tzu-Wang , ZENG, Yi
IPC分类号： H04B1/52
摘要： Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

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