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1. 发明申请

WO2011152744A3 METHOD AND APPARATUS FOR CONVERSION OF TIME INTERVAL TO DIGITAL WORD 审中-公开
标题翻译：用于将时间间隔转换为数字字的方法和装置
公开(公告)号：WO2011152744A3
公开(公告)日：2012-01-26
申请号：PCT/PL2011050021
申请日：2011-06-05
申请人： AKAD GORNICZO HUTNICZA , KOSCIELNIK DARIUSZ , MISKOWICZ MAREK
发明人： KOSCIELNIK DARIUSZ , MISKOWICZ MAREK
IPC分类号： G04F10/00
CPC分类号： G04F10/00 , G04F10/005
摘要： The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (Cn-1,..., C0) is characterized in that the time interval whose both start and end are detected by the control module (CM) is first mapped to a portion of electric charge delivered by the current source (I) and successively accumulated in the capacitors ((Cn-1,..., C0)) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the control module (CM) detects the end of the time interval, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1,..., b0) in the digital output word that correspond to the capacitors (Cn-1,..., C0) on which the reference voltage (UL) of a desired value has been obtained, and the value zero is assigned to the other bits.
摘要翻译：根据本发明的解决方案包括通过使用二进制比例电容器（Cn-1，...，C0）的阵列（A）将时间间隔转换成等于n的位数的数字字，其特征在于，由控制模块（CM）检测出开始和结束的时间间隔首先映射到由电流源（I）传送的电荷的一部分，并依次累积在电容器（（Cn-1， ...，C0）），并且当控制模块（CM）检测到时间间隔的结束时，电荷累积的电荷（Cn-1）从电容器（Cn-1）开始降低的顺序，在最近充电的电容器（Cx）中，通过使用电流源（I）连续传送到具有较低电容值的电容器。基于比较器（K1）和（K2）的输出信号，电荷转移的过程由控制模块（CM）控制，而不使用时钟，而值1被分配给这些位（bn-1 ，...，b0）对应于已经获得期望值的参考电压（UL）的电容器（Cn-1，...，C0）的数字输出字，并且分配值零到其他位。

2. 发明申请

WO2010114402A2 INTERFACE FOR COMMUNICATION BETWEEN SENSING DEVICES AND I2C BUS 审中-公开
标题翻译：感应设备与I2C总线之间的通信接口
公开(公告)号：WO2010114402A2
公开(公告)日：2010-10-07
申请号：PCT/PL2010/050014
申请日：2010-03-31
申请人： AKADEMIA GORNICZO-HUTNICZA IM. STANISLAWA STASZICA , MISKOWICZ, Marek , KOSCIELNIK, Dariusz
发明人： MISKOWICZ, Marek , KOSCIELNIK, Dariusz
IPC分类号： G06F13/38
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A conversion module contains an asynchronous analog-to-digital converter (AADC) with the output signal generated at irregular time intervals, whose output is connected to the input of the buffer memory module (BUF), and the output of the buffer memory module (BUF) is connected through the internal bus (BUS) simultaneously to the source address module (SADR), to the configuration registers module (REG), to the control module of the interface (CM), which the reference generator (RG) is connected to,and to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and moreover the control inputs/outputs (1, 2,...,8) of the control module (CM) are connected respectively to the asynchronous analog-to-digital converter (AADC), to the buffer memory module (BUF), to the source address module (SADR), to the configuration registers module (REG), to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and to the clock control module (SCM), and on the other hand, the transmitter/receiver module (SDM) output is connected through the controller (SDD) to the data line (SDA) of the I2C bus whose clock line (SCL) is connected through the other controller (SCD) to the clock control module (SCD) output, and what is more the write control output (9) of the asynchronous analog-to-digital converter (AADC) is connected to the write control input (10) of the buffer memory module (BUF).
摘要翻译：一个转换模块包含一个异步模数转换器（AADC），输出信号以不规则的时间间隔产生，其输出连接到缓冲存储器模块（BUF）的输入端，以及缓冲存储器模块（BUF）的输出通过内部总线（BUS）同时连接到源地址模块（SADR），配置寄存器模块（REG），连接到接口（CM）的控制模块，参考发生器（RG）连接到目标地址模块（DADR），选择寄存器模块（SELREG），发送器/接收器模块（SDM），并且控制输入/输出（1,2），...，8）分别连接到异步模数转换器（AADC），缓冲存储器模块（BUF），源地址模块（SADR），配置寄存器模块（REG）到目标地址模块（DADR），到选择寄存器模块发送器/接收器模块（SDM）和时钟控制模块（SCM），另一方面，发送器/接收器模块（SDM）输出通过控制器（SDD）连接到时钟线（SCL）通过另一个控制器（SCD）连接到时钟控制模块（SCD）输出的I2C总线的数据线（SDA），以及更多的异步模数转换器的写控制输出（9）模数转换器（AADC）连接到缓冲存储器模块（BUF）的写控制输入端（10）。

3. 发明申请

WO2010114402A3 INTERFACE FOR COMMUNICATION BETWEEN SENSING DEVICES AND I2C BUS 审中-公开
标题翻译：传感器与I2C总线之间的通讯接口
公开(公告)号：WO2010114402A3
公开(公告)日：2010-11-25
申请号：PCT/PL2010050014
申请日：2010-03-31
申请人： AKAD GORNICZO HUTNICZA , MISKOWICZ MAREK , KOSCIELNIK DARIUSZ
发明人： MISKOWICZ MAREK , KOSCIELNIK DARIUSZ
IPC分类号： G06F13/38
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A conversion module contains an asynchronous analog-to-digital converter (AADC) with the output signal generated at irregular time intervals, whose output is connected to the input of the buffer memory module (BUF), and the output of the buffer memory module (BUF) is connected through the internal bus (BUS) simultaneously to the source address module (SADR), to the configuration registers module (REG), to the control module of the interface (CM), which the reference generator (RG) is connected to,and to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and moreover the control inputs/outputs (1, 2,...,8) of the control module (CM) are connected respectively to the asynchronous analog-to-digital converter (AADC), to the buffer memory module (BUF), to the source address module (SADR), to the configuration registers module (REG), to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and to the clock control module (SCM), and on the other hand, the transmitter/receiver module (SDM) output is connected through the controller (SDD) to the data line (SDA) of the I2C bus whose clock line (SCL) is connected through the other controller (SCD) to the clock control module (SCD) output, and what is more the write control output (9) of the asynchronous analog-to-digital converter (AADC) is connected to the write control input (10) of the buffer memory module (BUF).
摘要翻译：转换模块包含异步模数转换器（AADC），其输出信号以不规则的时间间隔生成，其输出连接到缓冲存储器模块（BUF）的输入端，缓冲存储器模块 BUF）通过内部总线（BUS）同时连接到源地址模块（SADR），配置寄存器模块（REG）连接到参考发生器（RG）连接的接口（CM）的控制模块到目的地地址模块（DADR）到选择寄存器模块（SELREG）到发射机/接收机模块（SDM），以及控制输入/输出（1,2，...，8）控制模块（CM）分别连接到异步模数转换器（AADC），缓冲存储器模块（BUF），源地址模块（SADR），配置寄存器模块（REG），到目的地址模块（DADR）到选择寄存器模块（SELREG）发送器/接收器模块（SDM）和时钟控制模块（SCM），另一方面，发送器/接收器模块（SDM）输出通过控制器（SDD）连接到数据线（SDA）其时钟线（SCL）通过其他控制器（SCD）连接到时钟控制模块（SCD）输出的I2C总线，以及异步模数转换器（AADC）的写控制输出（9））连接到缓冲存储器模块（BUF）的写入控制输入（10）。

4. 发明申请

WO2008123786A2 METHOD AND APPARATUS FOR ANALOG-TO-DIGITAL CONVERSION USING ASYNCHRONOUS SIGMA-DELTA MODULATION 审中-公开
标题翻译：使用异步SIGMA-DELTA调制的模拟到数字转换的方法和装置
公开(公告)号：WO2008123786A2
公开(公告)日：2008-10-16
申请号：PCT/PL2008050006
申请日：2008-04-03
申请人： AKAD GORNICZO HUTNICZA , KOSCIELNIK DARIUSZ , MISKOWICZ MAREK
发明人： KOSCIELNIK DARIUSZ , MISKOWICZ MAREK
IPC分类号： H03M3/02
CPC分类号： H03M1/504 , H03M1/1215 , H03M3/43
摘要： The solution according to the invention consisting in the modulation of the analog signal using the asynchronous Sigma-Delta modulator, counting periods of the reference clock during each pulse of the previously obtained square wave and making the digital word available is characterized in that the square wave (z(t)) obtained in result of the modulation in the asynchronous Sigma-Delta modulator (ASDM) is subjected to conversion by counting the periods (T 0 ) of the reference clock (RG) during subsequent pulses of that square wave (z(t)) by means of the counting module (CTM), and then each word obtained representing the number of periods (T 0 ) of the reference clock (RG) counted during each given pulse of the square wave (z(t)) is recorded and stored in the intermediate buffer (TBUF); and the duration of the serial transmission of the digital word obtained in result of counting the periods of the reference clock (RG) during previous pulse of the square wave (z(t)) is simultaneously controlled by the control module (CM); and as soon as this transmission is completed, the content of the intermediate buffer (TBUF) is transferred to the transmitting buffer (TDR) of the apparatus; and after that a given digital word representing a given pulse of the squarewave (z(t)) is transmitted serially to the computer or to the communication network; then the cycle is repeated for the next pulse of the square wave (z(t)).
摘要翻译：根据本发明的解决方案包括使用异步Σ-Δ调制器对模拟信号的调制，在先前获得的方波的每个脉冲期间的参考时钟的计数周期和使数字字可用的特征在于方波在异步Σ-Δ调制器（ASDM）中的调制结果中获得的（z（t））通过在随后的时间内对参考时钟（RG）的周期（T 0）进行计数来进行转换通过计数模块（CTM），该方波（z（t））的脉冲，然后计算的表示参考时钟（RG）的周期数（T 0> 0）的每个字被计数在方波（z（t））的每个给定脉冲期间被记录并存储在中间缓冲器（TBUF）中; 由控制模块（CM）同时控制在方波（z（t））的先前脉冲期间对基准时钟（RG）的周期进行计数而得到的数字字的串行传输的持续时间。一旦该传输完成，中间缓冲器（TBUF）的内容被传送到设备的发送缓冲器（TDR）; 之后，表示方波（z（t））的给定脉冲的给定数字字被串行发送到计算机或通信网络; 那么对于方波的下一个脉冲（z（t）），重复该周期。

5. 发明申请

WO2011152743A3 METHOD AND APPARATUS FOR CONVERSION OF PORTION OF ELECTRIC CHARGE TO DIGITAL WORD 审中-公开
标题翻译：用于将电荷部分转换为数字字的方法和装置
公开(公告)号：WO2011152743A3
公开(公告)日：2012-02-02
申请号：PCT/PL2011050020
申请日：2011-06-05
申请人： AKAD GORNICZO HUTNICZA , KOSCIELNIK DARIUSZ , MISKOWICZ MAREK
发明人： KOSCIELNIK DARIUSZ , MISKOWICZ MAREK
IPC分类号： G04F10/00
CPC分类号： H03M1/12 , H03M1/466
摘要： The solution according to the invention consisting in conversion of a portion of electric charge to a digital word of a number of bits equal to n by the use of successive redistribution of charge in the array (A) of binary-scaled capacitors (Cn-1,...,Co) is characterized in that charge is first accumulated during the active state of the external gate signal on the gate signal input (InG) in the capacitors (Cn-1,...,Co) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the active state of the gate signal is terminated, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1,..., b0) in the digital output word that correspond to the capacitors (Cn-1,...,Co) on which the reference voltage (UL) of a desired value has been obtained, and the value zero is assigned to the other bits.
摘要翻译：根据本发明的解决方案包括通过使用二进制比例电容器（Cn-1）的阵列（A）中的电荷的连续重新分配将电荷的一部分转换成等于n的位数的数字字，...，Co）的特征在于，在电容器（Cn-1，...，Co）中的栅极信号输入（InG）上的外部栅极信号的有效状态期间，首先按照从阵列中具有最高电容值的电容器（Cn-1）开始降低电容，并且当门信号的有效状态终止时，最近充电的电容器（Cx）中累积的电荷通过使用电流源（I）到电容器的较低电容值。基于比较器（K1）和（K2）的输出信号，电荷转移的过程由控制模块（CM）控制，而不使用时钟，而值1分配给这些位（bn-1 ，...，b0）对应于已经获得了期望值的参考电压（UL）的电容器（Cn-1，...，Co）的数字输出字，并且分配值零到其他位。

6. 发明申请

WO2011152743A2 METHOD AND APPARATUS FOR CONVERSION OF PORTION OF ELECTRIC CHARGE TO DIGITAL WORD 审中-公开
标题翻译：用于将电荷部分转换为数字字的方法和装置
公开(公告)号：WO2011152743A2
公开(公告)日：2011-12-08
申请号：PCT/PL2011/050020
申请日：2011-06-05
申请人： AKADEMIA GORNICZO-HUTNICZA IM. STANISLAWA STASZICA , KOSCIELNIK, Dariusz , MISKOWICZ, Marek
发明人： KOSCIELNIK, Dariusz , MISKOWICZ, Marek
CPC分类号： H03M1/12 , H03M1/466
摘要： The solution according to the invention consisting in conversion of a portion of electric charge to a digital word of a number of bits equal to n by the use of successive redistribution of charge in the array (A) of binary-scaled capacitors (C n-1 ,...,C o ) is characterized in that charge is first accumulated during the active state of the external gate signal on the gate signal input (InG) in the capacitors (C n-1 ,...,C o ) in the order of decreasing capacitances starting from the capacitor (C n-1 ) having the highest capacitance value in the array, and when the active state of the gate signal is terminated, the charge accumulated in the capacitor (C x ) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (b n-1 ,..., b 0 ) in the digital output word that correspond to the capacitors (C n-1 ,...,C o ) on which the reference voltage (U L ) of a desired value has been obtained, and the value zero is assigned to the other bits.
摘要翻译：根据本发明的解决方案包括通过使用二进制比例电容器（Cn-1）的阵列（A）中的电荷的连续重新分配将电荷的一部分转换为等于n的数位的数字字，...，Co）的特征在于，在电容器（Cn-1，...，Co）中的栅极信号输入（InG）上的外部栅极信号的有效状态期间，首先按照从阵列中具有最高电容值的电容器（Cn-1）开始降低电容，并且当门信号的有效状态终止时，最近充电的电容器（Cx）中累积的电荷通过使用电流源（I）到电容器的较低电容值。基于比较器（K1）和（K2）的输出信号，电荷转移的过程由控制模块（CM）控制，而不使用时钟，而值1分配给这些位（bn-1 ，...，b0）对应于已经获得了期望值的参考电压（UL）的电容器（Cn-1，...，Co）的数字输出字，并且分配值零到其他位。

7. 发明申请

WO2010104408A1 METHOD OF CONTROLLING ACCESS OF DEVICES TO COMMUNICATION MEDIUM IN DISTRIBUTED NETWORKS 审中-公开
标题翻译：控制设备访问分布式网络中通信介质的方法
公开(公告)号：WO2010104408A1
公开(公告)日：2010-09-16
申请号：PCT/PL2010/050011
申请日：2010-03-13
申请人： AKADEMIA GORNICZO-HUTNICZA IM. STANISLAWA STASZICA , MISKOWICZ, Marek
发明人： MISKOWICZ, Marek
IPC分类号： H04L12/413
CPC分类号： H04L12/413
摘要： Each time before the packet transmission attempt, if the communication medium is detected to be idle, the prespecified fixed time interval equal to the minimum interpacket space is timed out during which the random numbers of time slots defining the order of media access are selected from the fixed number of slots of equal width using the pseudorandom number generator in every node where the probability of a selection of a particular slot is geometric with a characteristic parameter defined as the ratio of the probability of a selection of a given slot to the probability of a selection of the next slot, which changes from zero to one as a discrete function of the state of the node's counter, and after that the time interval of random delay corresponding to the selected random slot is assigned.
摘要翻译：在分组传输尝试之前的每一次，如果通信介质被检测为空闲，则等于最小分组空间的预先指定的固定时间间隔被超时，在该时间间隔内定义媒体接入顺序的时隙的随机数在每个节点中使用伪随机数发生器的固定数量的时隙，其中特定时隙的选择的概率是几何的，其特征参数被定义为给定时隙的选择的概率与一个给定时隙的概率的比率选择下一个时隙，其从零改变为1作为节点计数器的状态的离散函数，之后分配与所选择的随机时隙对应的随机延迟的时间间隔。

8. 发明申请

WO2011152745A3 METHOD AND APPARATUS FOR CONVERSION OF VOLTAGE VALUE TO DIGITAL WORD 审中-公开
标题翻译：用于将电压值转换为数字字的方法和装置
公开(公告)号：WO2011152745A3
公开(公告)日：2012-02-02
申请号：PCT/PL2011050022
申请日：2011-06-05
申请人： AKAD GORNICZO HUTNICZA , KOSCIELNIK DARIUSZ , MISKOWICZ MAREK
发明人： KOSCIELNIK DARIUSZ , MISKOWICZ MAREK
IPC分类号： G04F10/00
CPC分类号： H03M1/14 , H03M1/00 , H03M1/12 , H03M1/125 , H03M1/466 , H03M1/804
摘要： The solution according to the invention consisting in conversion of a voltage value to a digital word of a number of bits equal to n is characterized in that the converted voltage value is first mapped to a portion of electric charge accumulated in the sampling capacitor (C-n) during the active state of the signal on the trigger input (InS) and the accumulated charge portion is next successively redistributed by the use of the current source (I) in the array (A) of binary-scaled capacitors (Cn-1,..., C0) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array (A). The process of charge redistribution is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (bn-1,..., b0) in the digital output word that correspond to the capacitors (Cn-1,..., C0) on which the reference voltage (UL) of a desired value has been obtained, and the value zero is assigned to the other bits.
摘要翻译：将根据本发明的将电压值转换为等于n的位数的数字字的根据本发明的解决方案的特征在于，转换的电压值首先映射到在采样电容器（Cn）中累积的电荷的一部分，在触发输入（InS）的信号的有效状态下，并且累积电荷部分接下来通过使用二进制比例电容器（Cn-1，...）的阵列（A）中的电流源（I）重新分配。（C）），以从阵列（A）中具有最高电容值的电容器（Cn-1）开始降低电容的顺序。电荷再分配的过程由控制模块（CM）基于比较器（K1）和（K2）的输出信号控制，而不使用时钟，而值1被分配给这些位（bn-1 ，...，b0）对应于已经获得期望值的参考电压（UL）的电容器（Cn-1，...，C0）的数字输出字，并且分配值零到其他位。

9. 发明申请

WO2011152745A2 METHOD AND APPARATUS FOR CONVERSION OF VOLTAGE VALUE TO DIGITAL WORD 审中-公开
标题翻译：用于将电压值转换为数字字的方法和装置
公开(公告)号：WO2011152745A2
公开(公告)日：2011-12-08
申请号：PCT/PL2011/050022
申请日：2011-06-05
申请人： AKADEMIA GORNICZO-HUTNICZA IM. STANISLAWA STASZICA , KOSCIELNIK, Dariusz , MISKOWICZ, Marek
发明人： KOSCIELNIK, Dariusz , MISKOWICZ, Marek
CPC分类号： H03M1/14 , H03M1/00 , H03M1/12 , H03M1/125 , H03M1/466 , H03M1/804
摘要： The solution according to the invention consisting in conversion of a voltage value to a digital word of a number of bits equal to n is characterized in that the converted voltage value is first mapped to a portion of electric charge accumulated in the sampling capacitor (C- n ) during the active state of the signal on the trigger input (InS) and the accumulated charge portion is next successively redistributed by the use of the current source (I) in the array (A) of binary-scaled capacitors (C n-1 ,..., C 0 ) in the order of decreasing capacitances starting from the capacitor (C n-1 ) having the highest capacitance value in the array (A). The process of charge redistribution is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (b n-1 ,..., b 0 ) in the digital output word that correspond to the capacitors (C n-1 ,..., C 0 ) on which the reference voltage (U L) of a desired value has been obtained, and the value zero is assigned to the other bits.
摘要翻译：将根据本发明的将电压值转换为等于n的位数的数字字的根据本发明的解决方案的特征在于，转换的电压值首先映射到在采样电容器（Cn）中累积的电荷的一部分，在触发输入（InS）的信号的有效状态下，并且累积电荷部分接下来通过使用二进制比例电容器（Cn-1，...）的阵列（A）中的电流源（I）重新分配。（C）），以从阵列（A）中具有最高电容值的电容器（Cn-1）开始降低电容的顺序。电荷再分配的过程由控制模块（CM）基于比较器（K1）和（K2）的输出信号控制，而不使用时钟，而值1被分配给这些位（bn-1 ，...，b0）对应于已经获得期望值的参考电压（UL）的电容器（Cn-1，...，C0）的数字输出字，并且分配值零到其他位。

10. 发明申请

WO2011152744A2 METHOD AND APPARATUS FOR CONVERSION OF TIME INTERVAL TO DIGITAL WORD 审中-公开
标题翻译：用于将时间间隔转换为数字字的方法和装置
公开(公告)号：WO2011152744A2
公开(公告)日：2011-12-08
申请号：PCT/PL2011/050021
申请日：2011-06-05
申请人： AKADEMIA GORNICZO-HUTNICZA IM. STANISLAWA STASZICA , KOSCIELNIK, Dariusz , MISKOWICZ, Marek
发明人： KOSCIELNIK, Dariusz , MISKOWICZ, Marek
CPC分类号： G04F10/00 , G04F10/005
摘要： The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (C n-1 ,..., C 0 ) is characterized in that the time interval whose both start and end are detected by the control module (CM) is first mapped to a portion of electric charge delivered by the current source (I) and successively accumulated in the capacitors ((C n-1 ,..., C 0 )) in the order of decreasing capacitances starting from the capacitor (C n-1 ) having the highest capacitance value in the array, and when the control module (CM) detects the end of the time interval, the charge accumulated in the capacitor (C x ) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K1) and (K2) without the use of a clock while the value one is assigned to these bits (b n-1 ,..., b 0 ) in the digital output word that correspond to the capacitors (C n-1 ,..., C 0 ) on which the reference voltage (U L ) of a desired value has been obtained, and the value zero is assigned to the other bits.
摘要翻译：根据本发明的解决方案包括通过使用二进制比例电容器（Cn-1，...，C0）的阵列（A）将时间间隔转换成等于n的位数的数字字，其特征在于，由控制模块（CM）检测出开始和结束的时间间隔首先映射到由电流源（I）传送的电荷的一部分，并依次累积在电容器（（Cn-1， ...，C0）），并且当控制模块（CM）检测到时间间隔的结束时，电荷累积的电荷（Cn-1）从电容器（Cn-1）开始降低的顺序，在最近充电的电容器（Cx）中，通过使用电流源（I）连续传送到具有较低电容值的电容器。基于比较器（K1）和（K2）的输出信号，电荷转移的过程由控制模块（CM）控制，而不使用时钟，而值1被分配给这些位（bn-1 ，...，b0）对应于已经获得期望值的参考电压（UL）的电容器（Cn-1，...，C0）的数字输出字，并且分配值零到其他位。

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