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1. 发明申请

WO2009046202A2 METHOD AND APPARATUS FOR CONSERVING ENERGY STORED IN BYPASS CAPACITORS DURING DYNAMIC POWER COLLAPSE 审中-公开
标题翻译：在动力收敛期间保留旁路电容器储存的能量的方法和装置
公开(公告)号：WO2009046202A2
公开(公告)日：2009-04-09
申请号：PCT/US2008/078602
申请日：2008-10-02
申请人： QUALCOMM Incorporated , MICHALAK, Gerald Paul
发明人： MICHALAK, Gerald Paul
IPC分类号： H02J7/34
CPC分类号： H02J9/005 , H02M2001/0032 , Y02B70/16 , Y10T307/50
摘要： Energy stored in bypass capacitors in a portable device may be conserved when a power supply voltage is collapsed reducing the need to recharge the bypass capacitors and thereby saving power. A bypass charge saving circuit includes a bypass capacitor, a power source having an output supply voltage that is switchable, a load circuit of the portable device coupled to the output supply voltage, and the bypass capacitor operable to filter the output supply voltage. Also, a transistor switch is operable to decouple a discharge path of the bypass capacitor through the load circuit when the transistor switch is disabled. Further, a controller is operable to turn off the output supply voltage and the transistor switch in order to conserve energy stored in the bypass capacitor.
摘要翻译：存储在便携式设备中的旁路电容器中的能量可以在电源电压崩溃时被保存，从而减少对旁路电容器的再充电从而节省功率。旁路充电节电电路包括旁路电容器，具有可切换的输出电源电压的电源，耦合到输出电源电压的便携式设备的负载电路和用于滤波输出电源电压的旁路电容器。此外，当晶体管开关被禁用时，晶体管开关可操作用于通过负载电路去耦合旁路电容器的放电路径。此外，控制器可操作以关闭输出电源电压和晶体管开关，以便节省存储在旁路电容器中的能量。

2. 发明申请

WO2009046190A1 MEMORY CONTROLLER FOR PERFORMING MEMORY BLOCK INITIALIZATION AND COPY 审中-公开
标题翻译：用于执行存储块初始化和复制的存储器控制器
公开(公告)号：WO2009046190A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/078574
申请日：2008-10-02
申请人： QUALCOMM Incorporated , MICHALAK, Gerald Paul , HOFMANN, Richard Gerard , REMAKLUS, Perry Willmann Jr.
发明人： MICHALAK, Gerald Paul , HOFMANN, Richard Gerard , REMAKLUS, Perry Willmann Jr.
IPC分类号： G06F13/16
CPC分类号： G06F13/1668
摘要： A memory controller and methods for performing memory block initialization and copy functions with reduced bus traffic are disclosed. The memory controller can perform the memory initialization by receiving a start address of a memory, an end address of the memory and a fill value. The fill value is then written from the memory controller to the memory in a fill range of arbitrary length defined by the start address and end address.
摘要翻译：公开了一种用于执行具有减少的总线流量的存储器块初始化和复制功能的存储器控制器和方法。存储器控制器可以通过接收存储器的起始地址，存储器的结束地址和填充值来执行存储器初始化。然后将填充值从存储器控制器写入到由起始地址和结束地址定义的任意长度的填充范围内的存储器中。

3. 发明申请

WO2009015324A1 SYSTEM AND METHOD TO REDUCE DYNAMIC RAM POWER CONSUMPTION VIA THE USE OF VALID DATA INDICATORS 审中-公开
标题翻译：通过使用有效数据指示器来减少动态RAM功耗的系统和方法
公开(公告)号：WO2009015324A1
公开(公告)日：2009-01-29
申请号：PCT/US2008/071153
申请日：2008-07-25
申请人： QUALCOMM Incorporated , MICHALAK, Gerald, Paul , WOLFORD, Barry, Joe
发明人： MICHALAK, Gerald, Paul , WOLFORD, Barry, Joe
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40622
摘要： A DRAM or SDRAM component maintains an indicator that indicates whether or not an independently refreshable memory unit of a DRAM array, such as a row, contains valid data. When a refresh operation is directed to the associated memory, the refresh operation is suppressed if the memory does not contain valid data. Significant power savings may be realized by suppressing refresh operations directed to invalid data.
摘要翻译： DRAM或SDRAM组件保持指示器，其指示诸如行的DRAM阵列的独立可刷新的存储器单元是否包含有效数据。当刷新操作指向相关联的存储器时，如果存储器不包含有效数据，则刷新操作被抑制。可以通过抑制针对无效数据的刷新操作来实现显着的功率节省。

4. 发明申请

WO2005120023A1 INTEGRATED WIRELESS HEADSET 审中-公开
标题翻译：集成无线耳机
公开(公告)号：WO2005120023A1
公开(公告)日：2005-12-15
申请号：PCT/US2004/019891
申请日：2004-06-22
申请人： SONY ERICSSON MOBILE COMMUNICATIONS AB , MICHALAK, Gerald P.
发明人： MICHALAK, Gerald P.
IPC分类号： H04M1/05
CPC分类号： H04M1/0258 , G08B21/24 , H04M1/05 , H04M1/6066 , H04M2250/02
摘要： A mobile device integrates a wireless headset with the housing of a mobile terminal. In an exemplary embodiment, the housing of the mobile terminal includes a fastener for mechanically connecting the wireless headset to the housing. When the wireless headset is mechanically disconnected from the housing, a speaker and microphone associated with the wireless headset interfaces with the mobile terminal via a wireless interface. However, when the wireless headset mechanically connects to the housing, the speaker and microphone associated with the wireless headset mechanically and electrically connect to the housing and operate as the speaker and microphone for the mobile terminal. A detector circuit included in the mobile device also determines the position of the wireless headset relative to the mobile terminal, and may automatically select a wireless or electrical interface between the wireless headset and the mobile terminal based on the determined position.
摘要翻译：移动设备将无线耳机与移动终端的外壳集成。在示例性实施例中，移动终端的外壳包括用于将无线耳机机械地连接到外壳的紧固件。当无线耳机与壳体机械地断开连接时，与无线耳机相关联的扬声器和麦克风经由无线接口与移动终端接口。然而，当无线耳机机械地连接到外壳时，与无线耳机相关联的扬声器和麦克风机械地和电连接到壳体并作为用于移动终端的扬声器和麦克风进行操作。包括在移动设备中的检测器电路还确定无线耳机相对于移动终端的位置，并且可以基于所确定的位置自动选择无线耳机与移动终端之间的无线或电接口。

5. 发明申请

WO2013010164A1 METHODS AND APPARATUS FOR VOLTAGE SCALING 审中-公开
标题翻译：电压放大的方法和装置
公开(公告)号：WO2013010164A1
公开(公告)日：2013-01-17
申请号：PCT/US2012/046905
申请日：2012-07-16
申请人： QUALCOMM Incorporated , MICHALAK, Gerald Paul , BRIDGES, Jeffrey Todd
发明人： MICHALAK, Gerald Paul , BRIDGES, Jeffrey Todd
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/26 , Y02D10/172
摘要： Methods and apparatus for voltage scaling are provided. In an example, an operational limit of a processor is determined by varying a supply voltage to force a processor interrupt fault and/or a processor reset. A clock frequency and the supply voltage can be maintained substantially constant for a time duration. If these operational parameters do not force the processor interrupt fault and/or the processor reset, the supply voltage is varied again, and the clock frequency and the supply voltage are maintained substantially constant for a second time duration. The variation continues until initiation of the processor interrupt fault and/or the processor reset, at which time least one of a clock frequency, the supply voltage, and a temperature are recorded as an operational limit. After determining the operational limit, the supply voltage is adjusted to within the operational limit.
摘要翻译：提供了电压缩放的方法和装置。在一个示例中，通过改变供应电压来强制处理器中断故障和/或处理器复位来确定处理器的操作限制。时钟频率和电源电压可以在一段持续时间内保持基本恒定。如果这些操作参数不强制处理器中断故障和/或处理器复位，则电源电压再次变化，并且时钟频率和电源电压在第二持续时间内保持基本上恒定。该变化持续到处理器中断故障开始和/或处理器复位，此时将时钟频率，电源电压和温度中的至少一个记录为操作限制。确定运行极限后，将电源电压调整到运行极限内。

6. 发明申请

WO2008022288A1 METHOD AND APPARATUS FOR EXECUTING PROCESSOR INSTRUCTIONS BASED ON A DYNAMICALLY ALTERABLE DELAY 审中-公开
标题翻译：基于动态可变延迟执行处理器指令的方法和装置
公开(公告)号：WO2008022288A1
公开(公告)日：2008-02-21
申请号：PCT/US2007/076151
申请日：2007-08-16
申请人： QUALCOMM Incorporated , MICHALAK, Gerald Paul , DOCKSER, Kenneth Alan
发明人： MICHALAK, Gerald Paul , DOCKSER, Kenneth Alan
IPC分类号： G06F9/38
CPC分类号： G06F9/30145 , G06F9/3806 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3869 , G06F9/3877
摘要： Instruction execution delay is alterable after the system design has been finalized, thus enabling the system to dynamically account for various conditions that impact instruction execution. In some embodiments, the dynamic delay is determined by an application to be executed by the processing system. In other embodiments, the dynamic delay is determined by analyzing the history of previously executed instructions. In yet other embodiments, the dynamic delay is determined by assessing the processing resources available to a given application. Regardless, the delay may be dynamically altered on a per-instruction, multiple instruction, or application basis. Processor instruction execution may be controlled by determining a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions. Execution of the sets of instructions is delayed based on the corresponding delay value.
摘要翻译：指令执行延迟在系统设计完成后可以改变，从而使系统能够动态地考虑影响指令执行的各种条件。在一些实施例中，动态延迟由处理系统要执行的应用程序确定。在其他实施例中，通过分析先前执行的指令的历史来确定动态延迟。在其他实施例中，通过评估给定应用可用的处理资源来确定动态延迟。无论如何，延迟可以在每个指令，多个指令或应用程序的基础上动态地改变。处理器指令执行可以通过确定一个或多个指令的第一组的第一延迟值和第二组一个或多个指令的第二延迟值来控制。基于相应的延迟值来延迟指令集的执行。

7. 发明申请

WO2005036200A1 MOBILE TERMINALS AND METHODS FOR ESTIMATING GPS TIME BASED ON TIMING OF INFORMATION FROM A WIRELESS COMMUNICATION SYSTEM 审中-公开
标题翻译：基于无线通信系统信息时间估计GPS时间的移动终端和方法
公开(公告)号：WO2005036200A1
公开(公告)日：2005-04-21
申请号：PCT/US2004/016457
申请日：2004-05-20
申请人： SONY ERICSSON MOBILE COMMUNICATIONS AB , CAMP, William, O., Jr. , MICHALAK, Gerald , BLOEBAUM, L., Scott
发明人： CAMP, William, O., Jr. , MICHALAK, Gerald , BLOEBAUM, L., Scott
IPC分类号： G01S1/00
CPC分类号： G01S19/256
摘要： A mobile terminal generates an estimate of GPS time. The mobile terminal includes a cellular receiver, a GPS receiver, and a processor. The cellular receiver is configured to receive communication signals from cells in a wireless communication system. The GPS receiver receives GPS signals and determines a GPS time reference therefrom. The processor estimates a cell time reference from the received communication signals, and generates cell-to-GPS timing data that represents a time offset between the cell time reference and the GPS time reference. The processor then estimates GPS time based on a time indicator portion of a received communication signal and the cell-to-GPS timing data. The estimated GPS time may be used by the GPS receiver to acquire GPS signals.
摘要翻译：移动终端产生GPS时间的估计。移动终端包括蜂窝接收机，GPS接收机和处理器。蜂窝接收器被配置为从无线通信系统中的小区接收通信信号。 GPS接收机接收GPS信号并确定GPS时间参考。处理器从接收到的通信信号估计小区时间参考，并且生成表示小区时间基准和GPS时间基准之间的时间偏移的小区到GPS定时数据。然后，处理器基于接收到的通信信号的时间指示符部分和小区到GPS定时数据来估计GPS时间。 GPS接收机可以使用估计的GPS时间来获取GPS信号。

8. 发明申请

WO2013040271A1 VECTORIZATION OF MACHINE LEVEL SCALAR INSTRUCTIONS IN A COMPUTER PROGRAM DURING EXECUTION OF THE COMPUTER PROGRAM 审中-公开
标题翻译：计算机程序执行期间计算机程序中机器级标准说明的验证
公开(公告)号：WO2013040271A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/055250
申请日：2012-09-13
申请人： QUALCOMM Incorporated , MICHALAK, Gerald Paul , ESTES, Charles Dave
发明人： MICHALAK, Gerald Paul , ESTES, Charles Dave
IPC分类号： G06F9/32 , G06F9/30 , G06F9/455
CPC分类号： G06F9/3017 , G06F9/325
摘要： A method of operating a computer processor includes storing at least one machine level vector instruction in a memory and replacing a plurality of machine level scalar instructions in a computer program with the at least one machine level vector instruction during execution of the computer program based on execution addresses associated with the plurality of machine level scalar instructions and/or instruction opcodes associated with the plurality of machine level scalar instructions.
摘要翻译：一种操作计算机处理器的方法包括：在存储器中存储至少一个机器级矢量指令，并且在执行计算机程序期间，利用所述至少一个机器级矢量指令来替换计算机程序中的多个机器级标量指令与多个机器级标量指令相关联的地址和/或与多个机器级标量指令相关联的指令操作码。

9. 发明申请

WO2012100032A1 DYNAMIC VIDEO SWITCHING 审中-公开
标题翻译：动态视频切换
公开(公告)号：WO2012100032A1
公开(公告)日：2012-07-26
申请号：PCT/US2012/021841
申请日：2012-01-19
申请人： QUALCOMM INCORPORATED , FANG, Xin , SHI, Wei , MICHALAK, Gerald Paul
发明人： FANG, Xin , SHI, Wei , MICHALAK, Gerald Paul
IPC分类号： H04N21/442 , H04N21/426
CPC分类号： H04N21/4424 , H04N21/42607
摘要： In an example, a dynamic codec allocation method is provided. The method includes receiving a plurality of datastreams and determining a respective codec loading factor for each of the datastreams. The datastreams are assigned to codecs, in order by respective codec loading factor, starting with the highest respective codec loading factor. Initially, the datastreams are assigned to a hardware codec, until the hardware codec is loaded to substantially maximum capacity. If the hardware codec is loaded to substantially maximum capacity, the remaining datastreams are assigned to a software codec. As new datastreams are received, the method repeats, and previously-assigned datastreams can be reassigned from a hardware codec to a software codec, and vice versa, based on their relative codec loading factors.
摘要翻译：在一个示例中，提供了动态编解码器分配方法。该方法包括接收多个数据流并确定每个数据流的相应的编解码器加载因子。数据流被分配到编解码器，按照相应的编解码器加载因子顺序，从最高的相应的编解码器加载因子开始。最初，数据流被分配到硬件编解码器，直到硬件编解码器被加载到基本上最大的容量。如果硬件编解码器被加载到基本上最大的容量，剩余的数据流被分配给软件编解码器。当接收到新的数据流时，该方法重复，并且可以基于它们的相对编解码器加载因子将先前分配的数据流从硬件编解码器重新分配到软件编解码器，反之亦然。

10. 发明申请

WO2010083326A1 CURRENT SENSING MECHANISM 审中-公开
标题翻译：电流感应机构
公开(公告)号：WO2010083326A1
公开(公告)日：2010-07-22
申请号：PCT/US2010/021066
申请日：2010-01-14
申请人： QUALCOMM INCORPORATED , MICHALAK, Gerald, Paul
发明人： MICHALAK, Gerald, Paul
IPC分类号： G01R15/18 , G01R31/28
CPC分类号： G01R31/2884 , G01R15/181 , G01R15/202 , G01R31/3025
摘要： A current sensing mechanism for use in an integrated circuit is described. In one embodiment, the integrated circuit comprises a voltage supply rail and a current sensor coupled to that voltage supply rail such that the current sensor determines the current passing through the voltage supply rail. Leads attached to the current sensor can be monitored to obtain measurements that permit determination of the current.
摘要翻译：描述了一种用于集成电路的电流检测机构。在一个实施例中，集成电路包括电压供应轨和耦合到该电压供应轨的电流传感器，使得电流传感器确定通过电压供应轨的电流。可以监控连接到电流传感器的引线，以获得允许确定电流的测量。

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