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1. 发明申请

WO2009046190A1 MEMORY CONTROLLER FOR PERFORMING MEMORY BLOCK INITIALIZATION AND COPY 审中-公开
标题翻译：用于执行存储块初始化和复制的存储器控制器
公开(公告)号：WO2009046190A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/078574
申请日：2008-10-02
申请人： QUALCOMM Incorporated , MICHALAK, Gerald Paul , HOFMANN, Richard Gerard , REMAKLUS, Perry Willmann Jr.
发明人： MICHALAK, Gerald Paul , HOFMANN, Richard Gerard , REMAKLUS, Perry Willmann Jr.
IPC分类号： G06F13/16
CPC分类号： G06F13/1668
摘要： A memory controller and methods for performing memory block initialization and copy functions with reduced bus traffic are disclosed. The memory controller can perform the memory initialization by receiving a start address of a memory, an end address of the memory and a fill value. The fill value is then written from the memory controller to the memory in a fill range of arbitrary length defined by the start address and end address.
摘要翻译：公开了一种用于执行具有减少的总线流量的存储器块初始化和复制功能的存储器控制器和方法。存储器控制器可以通过接收存储器的起始地址，存储器的结束地址和填充值来执行存储器初始化。然后将填充值从存储器控制器写入到由起始地址和结束地址定义的任意长度的填充范围内的存储器中。

2. 发明申请

WO2005071557A2 A MULTIPLE ADDRESS TWO CHANNEL BUS STRUCTURE 审中-公开
标题翻译：多地址双通道总线结构
公开(公告)号：WO2005071557A2
公开(公告)日：2005-08-04
申请号：PCT/US2005/001590
申请日：2005-01-20
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard Gerard , GANASAN, Jaya Prakash Subramaniam , LOWERY, Thomas John , REMAKLUS, Perry Willmann, Jr.
发明人： HOFMANN, Richard Gerard , GANASAN, Jaya Prakash Subramaniam , LOWERY, Thomas John , REMAKLUS, Perry Willmann, Jr.
IPC分类号： G06F13/42
CPC分类号： G06F13/423 , G06F13/4243
摘要： A processing system is disclosed with a sending component and a receiving component connected by a multiple address two channel bus. The sending device may broadcast on the first channel of the bus read address information comprising a plurality of read address locations, write address information comprising a plurality of write address locations, and write data. The sending component may also broadcast the read and write address information multiple address locations at a time. The receiving component may store the write data broadcast on the first channel based on the write address information, retrieve the read data from the receiving component based on the read address information, and broadcasting the retrieved read data on the second channel of the bus.
摘要翻译：公开了一种具有通过多地址双通道总线连接的发送组件和接收组件的处理系统。发送设备可以在总线的第一信道上广播包括多个读取地址位置的读取地址信息，包括多个写入地址位置的写入地址信息以及写入数据。发送组件也可以一次广播读取和写入地址信息多个地址位置。接收组件可以基于写地址信息存储在第一信道上广播的写数据，基于读地址信息从接收组件检索读数据，并且在总线的第二信道上广播检索到的读数据。 / p>

3. 发明申请

WO2007085005A2 METHOD OF ASSOCIATING GROUPS OF CLASSIFIED SOURCE ADDRESSES WITH VIBRATION PATTERNS 审中-公开
标题翻译：使用振动模式分类分类源地址组的方法
公开(公告)号：WO2007085005A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/060805
申请日：2007-01-19
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard Gerard , MICHALAK, Gerald Paul , WOLFORD, Barry Joe
发明人： HOFMANN, Richard Gerard , MICHALAK, Gerald Paul , WOLFORD, Barry Joe
IPC分类号： H04M1/57 , H04M19/04
CPC分类号： H04M19/04 , H04M1/57 , H04M1/72547 , H04M19/044 , H04M19/047
摘要： In a meeting or group event, people having a portable device, such as a cell phone or pager, may wish to be discretely notified when an important message is received, an urgent call comes in from a selected person or a selected group of people, or to be alerted to an upcoming important event without any audible alert to disturb the meeting or group event. To convey such a notification, a tactile alert is provided by vibrating the portable device according to a unique vibration pattern associated with the received communication. When a communication is received, a group identification (ID) is assigned based on the communication being a member of a classified group of source addresses. The portable device associates the group ID with a unique vibration pattern. To provide the alert, the portable device is vibrated according to the unique vibration pattern.
摘要翻译：在会议或小组活动中，具有诸如蜂窝电话或寻呼机的便携式设备的人可能希望在收到重要消息时离散地通知来自所选择的人或所选人群的紧急呼叫，或者提醒未来的重要事件而没有任何可听见的警报来打扰会议或团体活动。为了传达这种通知，通过根据与接收的通信相关联的唯一振动模式振动便携式设备来提供触觉警报。当接收到通信时，基于作为分类的源地址组的成员的通信来分配组标识（ID）。便携式设备将组ID与唯一的振动模式相关联。为了提供警报，便携式设备根据独特的振动模式而振动。

4. 发明申请

WO2012103558A1 BUS CLOCK FREQUENCY SCALING FOR A BUS INTERCONNECT AND RELATED DEVICES, SYSTEMS, AND METHODS 审中-公开
标题翻译：总线互连的总线时钟频率和相关设备，系统和方法
公开(公告)号：WO2012103558A1
公开(公告)日：2012-08-02
申请号：PCT/US2012/023194
申请日：2012-01-30
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard Gerard , GANASAN, Jaya Prakash Subramaniam , LEWIS, Brandon Wayne
发明人： HOFMANN, Richard Gerard , GANASAN, Jaya Prakash Subramaniam , LEWIS, Brandon Wayne
IPC分类号： G06F13/40 , G06F1/04 , G06F1/32
CPC分类号： G06F13/4022 , G06F1/06 , G06F1/3209 , G06F1/324 , Y02D10/126 , Y02D10/151
摘要： Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods are disclosed. In one embodiment, the bus interconnect comprises an interconnect network configurable to connect a master port(s) to a slave port(s). A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic communicated over the master port(s) and the slave port(s). The controller is further configured to scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master port(s) and/or the slave port(s) meets respective bandwidth condition(s), and/or if the latency of the master port(s) meets a respective latency condition(s) for the master port(s). The master port(s) and/or slave port(s) can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power.
摘要翻译：公布了总线互连及相关设备，系统和方法的总线时钟频率缩放。在一个实施例中，总线互连包括可配置为将主端口连接到从端口的互连网络。总线互连时钟信号对互连网络进行时钟。控制器被配置为接收与通过主端口和从端口传送的业务相关的带宽信息。如果主端口和/或从端口的带宽满足相应的带宽条件，则控制器进一步被配置为扩展（例如，增加或减少）总线互连时钟信号的频率，以及 /或如果主端口的延迟满足主端口的相应等待时间条件。主端口和/或从端口也可以被重新配置以响应总线互连时钟信号的频率变化，以优化性能并节省功率。

5. 发明申请

WO2011003083A1 TEMPERATURE COMPENSATING ADAPTIVE VOLTAGE SCALERS (AVSs), SYSTEMS, AND METHODS 审中-公开
标题翻译：温度补偿自适应电压调节器（AVS），系统和方法
公开(公告)号：WO2011003083A1
公开(公告)日：2011-01-06
申请号：PCT/US2010/040946
申请日：2010-07-02
申请人： QUALCOMM INCORPORATED , HANSQUINE, David W. , HOFMANN, Richard Gerard , MOORE, Richard Alan
发明人： HANSQUINE, David W. , HOFMANN, Richard Gerard , MOORE, Richard Alan
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variations to avoid or reduce voltage margin. In one embodiment, an AVS module is provided and coupled to a database. The database is configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The database allows rapid voltage level decisions. In one embodiment, a voltage offset is added to a voltage level retrieved from the database corresponding to a target operating frequency of the functional circuit(s). In another embodiment, a voltage level is retrieved from the database corresponding to a target operating frequency for and temperature level of the functional circuit(s). The AVS module may be partially or fully controllable by software that consults the database to make voltage level decisions.
摘要翻译：自适应电压缩放器（AVS），系统和相关方法被公开。 AVS被配置为基于目标工作频率和延迟变化自适应地调整为功能电路供电的电压电平，以避免或减少电压裕度。在一个实施例中，提供AVS模块并耦合到数据库。数据库被配置为存储功能电路的各种工作频率的电压电平，以避免或减少电压裕度。数据库允许快速的电压电平决定。在一个实施例中，电压偏移被添加到从数据库检索的电压电平，该电压电平对应于功能电路的目标工作频率。在另一个实施例中，从对应于功能电路的目标工作频率和温度水平的数据库检索电压电平。 AVS模块可以部分或完全由可以参考数据库的软件来控制，以进行电压电平决定。

6. 发明申请

WO2007106698A2 EFFICIENT EXECUTION OF MEMORY BARRIER BUS COMMANDS 审中-公开
标题翻译：内存障碍物总线命令的有效执行
公开(公告)号：WO2007106698A2
公开(公告)日：2007-09-20
申请号：PCT/US2007/063510
申请日：2007-03-07
申请人： QUALCOMM INCORPORATED , SULLIVAN, James Edward, Jr. , GANASAN, Jaya Prakash Subramaniam , HOFMANN, Richard Gerard
发明人： SULLIVAN, James Edward, Jr. , GANASAN, Jaya Prakash Subramaniam , HOFMANN, Richard Gerard
IPC分类号： G06F9/38
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译：本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。

7. 发明申请

WO2007101170A1 AUXILIARY WRITES OVER ADDRESS CHANNEL 审中-公开
标题翻译：地址通道辅助写
公开(公告)号：WO2007101170A1
公开(公告)日：2007-09-07
申请号：PCT/US2007/062830
申请日：2007-02-26
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard Gerard , LOHMAN, Terry
发明人： HOFMANN, Richard Gerard , LOHMAN, Terry
IPC分类号： G06F13/42
CPC分类号： G06F13/4282 , G06F13/4265
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.
摘要翻译：公开了一种用于通过总线在处理系统中进行通信的处理系统和方法。处理系统包括接收装置，具有第一，第二和第三信道的总线，以及发送装置，被配置为在第一信道上寻址接收装置，并且从第二信道上的接收装置读取有效载荷，发送装置为还被配置为在所述第一和第三信道之间选择以将有效载荷写入所述接收设备。

8. 发明申请

WO2012048327A1 MEMORY CONTROLLERS, SYSTEMS, AND METHODS FOR APPLYING PAGE MANAGEMENT POLICIES BASED ON STREAM TRANSACTION INFORMATION 审中-公开
标题翻译：基于流动交易信息应用页面管理政策的记忆控制器，系统和方法
公开(公告)号：WO2012048327A1
公开(公告)日：2012-04-12
申请号：PCT/US2011/055637
申请日：2011-10-10
申请人： QUALCOMM INCORPORATED , SHIRLEN, Martyn Ryan , HOFMANN, Richard Gerard , SCHAFFER, Mark Michael
发明人： SHIRLEN, Martyn Ryan , HOFMANN, Richard Gerard , SCHAFFER, Mark Michael
IPC分类号： G06F13/16
CPC分类号： G06F13/1689 , G06F12/0215
摘要： Memory controllers, systems, methods, and computer-readable mediums for applying a page management policy(ies) based on stream transaction information are disclosed. In one embodiment, a memory controller is provided and configured to receive memory access requests for stream transactions. The memory controller is configured to perform a memory access to a memory page(s) in memory included in the stream transaction. The controller is further configured to apply a page management policy(ies) to the memory page(s) in memory based on information related to the stream transactions. In this manner, the page management policy(ies) can be configured to utilize page open policies for efficiency that stream transactions may facilitate, but while also recognizing and taking into consideration in the page management policy latency issues that can arise when the memory controller is handling memory access requests from different devices.
摘要翻译：公开了用于基于流交易信息应用页面管理策略的内存控制器，系统，方法和计算机可读介质。在一个实施例中，存储器控制器被提供并被配置为接收用于流事务的存储器访问请求。存储器控制器被配置为对包含在流事务中的存储器中的存储器页执行存储器访问。控制器还被配置为基于与流事务相关的信息将页面管理策略应用于存储器中的存储器页面。以这种方式，页面管理策略可以被配置为利用页面打开的策略来实现流交易可以促进的效率，而且在存储器控制器是可能出现的页面管理策略延迟问题的同时还识别和考虑处理来自不同设备的存储器访问请求。

9. 发明申请

WO2010030581A1 METHOD FOR SECURELY COMMUNICATING INFORMATION ABOUT THE LOCATION OF A COMPROMISED COMPUTING DEVICE 审中-公开
标题翻译：用于安全地传达关于压缩计算设备的位置的信息的方法
公开(公告)号：WO2010030581A1
公开(公告)日：2010-03-18
申请号：PCT/US2009/056074
申请日：2009-09-04
申请人： QUALCOMM Incorporated , SHIRLEN, Martyn Ryan , HOFMANN, Richard Gerard
发明人： SHIRLEN, Martyn Ryan , HOFMANN, Richard Gerard
IPC分类号： G06F21/00 , G06F21/02
CPC分类号： H04L63/1441 , G06F21/55 , G06F21/554 , G06F21/73 , G06F21/88
摘要： A method for securely reporting location information after an attack on a computing device is presented. Such information may be reported to a requesting entity in a manner almost transparent to an attacker. Several exemplary embodiments of systems wherein the method may be used are presented.
摘要翻译：提出了一种在对计算设备进行攻击后安全地报告位置信息的方法。这样的信息可以以对攻击者几乎透明的方式被报告给请求实体。呈现了可以使用该方法的系统的几个示例性实施例。

10. 发明申请

WO2007101134A1 COOPERATIVE WRITES OVER THE ADDRESS CHANNEL OF A BUS 审中-公开
标题翻译：总线地址通道上的合作写作
公开(公告)号：WO2007101134A1
公开(公告)日：2007-09-07
申请号：PCT/US2007/062761
申请日：2007-02-23
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard Gerard , LOHMAN, Terence J.
发明人： HOFMANN, Richard Gerard , LOHMAN, Terence J.
IPC分类号： G06F13/42
CPC分类号： G06F13/4243 , G06F13/42 , G06F13/4273
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
摘要翻译：公开了一种用于通过总线在处理系统中通信的处理系统和方法。处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是还被配置为将所述有效负载的第一部分写入所述第一信道上的所述接收设备，并且将所述有效载荷的第二部分写入所述第三信道上的接收设备。

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