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1. 发明申请

WO1991010200A1 PARALLEL PROCESSOR MEMORY SYSTEM 审中-公开
标题翻译：并行处理器存储系统
公开(公告)号：WO1991010200A1
公开(公告)日：1991-07-11
申请号：PCT/US1991000078
申请日：1991-01-04
申请人： MASPAR COMPUTER CORPORATION
发明人： MASPAR COMPUTER CORPORATION , KIM, Won, S. , BULFER, David, M. , NICKOLLS, John, R. , BLANK, W., Thomas , FIGEL, Hannes
IPC分类号： G06F15/409
CPC分类号： G06F11/1044 , G06F15/17393 , G06F15/8015
摘要： A massively parallel processor includes a plurality of clusters (40). Each cluster includes processor elements (50.00-50.15) ("PEs") and a cluster memory (54). Each PE (200) has an address register (206), stage register (251), error register (310), enable flag (336) memory flag (338), and grant request flag (211). A cluster data bus (225) and error bus (302, 304) connects each stage register and error register of the cluster to memory (260). The grant request flags of the cluster are interconnected by a polling network (362, 364), which polls one grant request flag at a time. In response to a signal on polling network (362, 364) and the state of the memory flag (338), grant request flag (211) determines an I/O operation between data register (251) and cluster memory (260) over cluster data bus (255). Data and error bits are associated with respective processor elements (200). Sequential memory operations (110 - 113) proceed in parallel with parallel processor operations (102 - 109) and may be queued. In direct address mode, a PE (200) addresses its own address space by appending its PE number (203) to a broadcast partial address furnished over a broadcast bus (250). The PE number (203) is furnished on a cluster address bus (246). In indirect address mode, PE addresses its own address space or that of other PEs in its cluster by locally calculating a partial address, then appending to it its own PE number (203) or that of another PE in its cluster. The full address is furnished over the cluster address bus (246).
摘要翻译：大规模并行处理器包括多个簇（40）。每个集群包括处理器元件（50.00-50.15）（“PE”）和集群存储器（54）。每个PE（200）具有地址寄存器（206），级寄存器（251），错误寄存器（310），使能标志（336）存储器标志（338）和授权请求标志（211）。集群数据总线（225）和错误总线（302,304）将集群的每个级寄存器和错误寄存器连接到存储器（260）。集群的授权请求标志由轮询网络（362,364）互连，轮询网络（362,364）一次轮询一个授权请求标志。响应于轮询网络（362,364）上的信号和存储器标志（338）的状态，授权请求标志（211）确定簇上的数据寄存器（251）和集群存储器（260）之间的I / O操作数据总线（255）。数据和错误位与相应的处理器元件（200）相关联。顺序存储器操作（110-113）与并行处理器操作（102-109）并行进行并且可以排队。在直接地址模式中，PE（200）通过将其PE号码（203）附加到通过广播总线（250）提供的广播部分地址来寻址其自己的地址空间。 PE号码（203）设置在集群地址总线（246）上。在间接寻址模式下，PE通过本地计算部分地址来寻址其自身的地址空间或其簇中的其他PE，然后将其自身的PE号（203）或其簇中的另一个PE附加到其上。整个地址通过集群地址总线（246）提供。

2. 发明申请

WO1991010197A1 SCALABLE INTER-PROCESSOR AND PROCESSOR TO I/O MESSAGING SYSTEM FOR PARALLEL PROCESSING ARRAYS 审中-公开
标题翻译：可分级处理器和处理器到并行处理阵列的I / O消息传递系统
公开(公告)号：WO1991010197A1
公开(公告)日：1991-07-11
申请号：PCT/US1991000077
申请日：1991-01-04
申请人： MASPAR COMPUTER CORPORATION
发明人： MASPAR COMPUTER CORPORATION , NICKOLLS, John, R. , ZAPISEK, John , KIM, Won, S. , KALB, Jeffrey, C. , BLANK, W., Thomas , WEGBREIT, Eliot , VAN HORN, Kevin
IPC分类号： G06F15/00
CPC分类号： G06F15/17393
摘要： A massively parallel computer system (500) is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O (1700) messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors (700) of the massively parallel system and the global router network are also disclosed.

3. 发明申请

WO1994001826A1 SYSTEMS AND METHODS FOR PLANNING AND SIMULATION 审中-公开
标题翻译：用于规划和模拟的系统和方法
公开(公告)号：WO1994001826A1
公开(公告)日：1994-01-20
申请号：PCT/US1993006027
申请日：1993-06-23
申请人： MASPAR COMPUTER CORPORATION
发明人： MASPAR COMPUTER CORPORATION , BROWN, John, S. , BLANK, William, T. , HOLT, Mark, W.
IPC分类号： G06F15/22
CPC分类号： G06Q10/06 , G06F17/5009
摘要： A fast system addressing the same problem as MRP-II is described which is suitable for a multi-processor computer. The system performs both material requirements planning and capacity resource planning. Material requirements planning is performed by the multi-processor computer (504) as follows. A process tree incorporating a bill of materials as well as routing information is ranked, and the orders for the materials of each rank are exploded before any order for any higher rank material is exploded. Separate processors (536) explode in parallel the orders for separate materials of the same rank. Capacity Resource Planning is performed in parallel, a separate processor (536) planning the capacity of a separate work center. Simulation of material production is performed in parallel for each rank, separate processors simulating the production of separate materials of the same rank. The simulation is performed starting with the highest rank and proceeding in sequence to the lowest rank. Simulation of work center schedules is performed in parallel similarly to the MRP-II method described. The invention is applicable also to Just-in-Time manufacturing, and to planning and simulation in transportation industries.
摘要翻译：描述了适用于多处理器计算机的解决与MRP-II相同问题的快速系统。系统执行物料需求计划和容量资源规划。物料需求计划由多处理器计算机（504）执行如下。排列了包含材料单和路线信息的流程树，并且在任何更高等级的材料的任何订单爆炸之前，每个等级的材料的顺序都会被分解。独立的处理器（536）并行地爆发了相同等级的单独材料的订单。容量资源规划是并行执行的，一个单独的处理器（536）规划了单独工作中心的容量。材料生产的模拟对于每个级别并行执行，模拟生产相同等级的单独材料的单独处理器。以最高等级开始进行模拟，并按顺序进行到最低等级。类似于所描述的MRP-II方法并行地执行工作中心计划的模拟。本发明也适用于即时制造，以及运输行业的规划和模拟。

4. 发明申请

WO1993011496A1 INPUT/OUTPUT SYSTEM FOR PARALLEL PROCESSING ARRAYS 审中-公开
标题翻译：用于并行处理阵列的输入/输出系统
公开(公告)号：WO1993011496A1
公开(公告)日：1993-06-10
申请号：PCT/US1992010224
申请日：1992-12-02
申请人： MASPAR COMPUTER CORPORATION
发明人： MASPAR COMPUTER CORPORATION , NICKOLLS, John, R. , KIM, Won, S. , ZAPISEK, John , BLANK, William, T.
IPC分类号： G06F15/16
CPC分类号： G06F15/8007 , G06F15/17393
摘要： A massively parallel processor includes an array of processor element (20), or PEs, and a multi-stage router interconnection network (30), which is used both for I/O communications and for simultaneous PE to PE communications. The I/O system (10) for the massively parallel processor is based on a globally shared addressable I/O RAM buffer memory (50) that has parallel address and data buses (52) to the I/O devices (80, 82) and other parallel address and data buses (42) which are coupled to a router I/O element array (40). The router I/O element array is in turn coupled to the bit-serial router ports (e.g. S2 ^_O ^_XO) of the second stage (430) of the router interconnection network. The router I/O array provides the corner turn conversion between the massive array of bit-serial router lines (32) and the relatively few parallel buses (52) to the I/O devices.

5. 发明申请

WO1991010198A1 ROUTER CHIP WITH QUAD-CROSSBAR AND HYPERBAR PERSONALITIES 审中-公开
标题翻译：带有十字架和高性能个人的路由器芯片
公开(公告)号：WO1991010198A1
公开(公告)日：1991-07-11
申请号：PCT/US1991000094
申请日：1991-01-05
申请人： MASPAR COMPUTER CORPORATION
发明人： MASPAR COMPUTER CORPORATION , ZAPISEK, John
IPC分类号： G06F15/16
CPC分类号： G06F15/17393 , G06F11/1423 , G06F11/22 , H04L49/101 , H04L49/555
摘要： A router circuit (130) is made configurable as either a crossbar switch or a hyperbar switch by dividing the router chip into sections (sections A-D), where each section is associated with a group of input terminals, and wherein various grant circuits (272) within each of the sections have enable/disable input terminals (506) connected by controllable switches (400) to either enable/disable output terminals of grant circuits in an adjacent section (hyperbar personaly) or to fixed logic levels (crossbar personality). In the crossbar configuration, for each input terminal of a section, only one grant circuit (272) per channel is enabled. Each of the sections has a different set of grant circuits enabled per channel so that two sections can not access a same output terminal of the router chip. In the hyperbar configuration, the sections are made transparent, and grant circuits are enabled or disabled depending on output wire availability. Additionally, the router circuit contains novel routing address bit and protocol bit circuitry (252, 258) as well as novel diagnostic circuitry (584) for detecting broken wires (550) between router circuits.
摘要翻译：通过将路由器芯片分成部分（部分AD），每个部分与一组输入终端相关联，路由器电路（130）可配置为交叉开关或超级开关，并且其中各种授权电路（272）在每个部分内，具有通过可控开关（400）连接的启用/禁用输入端子（506），以使得/禁用相邻部分（超级棒人）中的授权电路的输出端或者固定逻辑电平（交叉开关人格）。在交叉开关配置中，对于每个输入端子，每个通道仅允许一个授权电路（272）。每个部分具有每个通道启用的不同的授权电路集合，使得两个部分不能访问路由器芯片的相同输出端子。在超高速配置中，这些部分是透明的，并且根据输出线路可用性启用或禁用授权电路。此外，路由器电路包含新颖的路由地址位和协议位电路（252,258）以及用于检测路由器电路之间的断线（550）的新型诊断电路（584）。

6. 发明申请

WO1991010183A1 SYSTEM FOR INTERCONNECTING ROUTER ELEMENTS WITH PARALLEL COMPUTER 审中-公开
标题翻译：用于并行计算机的路由器元件互连的系统
公开(公告)号：WO1991010183A1
公开(公告)日：1991-07-11
申请号：PCT/US1991000093
申请日：1991-01-04
申请人： MASPAR COMPUTER CORPORATION
发明人： MASPAR COMPUTER CORPORATION , TAYLOR, Stuart, A.
IPC分类号： G06F03/00
CPC分类号： G06F13/4022 , G06F15/17393
摘要： A network and method for interconnecting a plurality of router elements (11-13, 20-23, 30-33) in a parallel computer. The network forms a routing system (5) for routing data from source processing elements (PE1 - PE64) to destination processing elements. The input lines (IL-101 to IL-116) and output lines (1A1 to 1D4) of each router chip (100) are prioritized. Higher priority output lines (2A1, 2A2) from a given output group (A) of a first routing element (10) are connected to low priority input lines (415, 410) of a second routing element (20) and lower priority output lines (2A3, 2A4) from the output group (A) of the first routing element (10) are connected to higher priority input lines (401, 408) of the second routing element (20).

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