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1. 发明申请

WO2010137899A2 LEADFRAME AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译： LEADFRAME及其制造方法
公开(公告)号：WO2010137899A2
公开(公告)日：2010-12-02
申请号：PCT/KR2010003384
申请日：2010-05-27
申请人： LG INNOTEK CO LTD , EOM SAI RAN , LEE HYUNG EUI , PARK CHUNG SIK , CHUN HYUN A , YOON HYE SUN
发明人： EOM SAI RAN , LEE HYUNG EUI , PARK CHUNG SIK , CHUN HYUN A , YOON HYE SUN
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/49861 , H01L21/4832 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49 , H01L2224/85411 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2224/85471 , H01L2224/85871 , H01L2924/00014 , H01L2924/01005 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/3025 , H01L2224/45099 , H01L2924/00012
摘要： Disclosed is a leadframe. The leadframe comprises a die pad part, at least one lead part, and at least one supporting part. A semiconductor chip is mounted on a first surface of the leadframe at the die pad. The at least one lead part electrically connects the semiconductor chip to at least one external circuit. The at least one supporting part is adjacent to a second surface opposited the first surface, includes an insulating material, and insulates the at least one lead part from each other.
摘要翻译：披露的是引线框架。引线框架包括芯片焊盘部分，至少一个引线部分和至少一个支撑部分。半导体芯片安装在引线框架的芯片焊盘的第一表面上。至少一个引线部分将半导体芯片电连接到至少一个外部电路。所述至少一个支撑部分邻近与所述第一表面相对的第二表面，包括绝缘材料并使所述至少一个引线部分彼此绝缘。

2. 发明申请

WO2010036051A2 STRUCTURE AND MANUFACTURE METHOD FOR MULTI-ROW LEAD FRAME AND SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：用于多引线框架和半导体封装的结构和制造方法
公开(公告)号：WO2010036051A2
公开(公告)日：2010-04-01
申请号：PCT/KR2009005481
申请日：2009-09-25
申请人： LG INNOTEK CO LTD , KIM JI YUN , SHIN HYUN SUB , LEE SUNG WON , LEE HYUNG EUI , SEO YEONG UK , RYU SUNG WUK , LEE HYUK SOO
发明人： KIM JI YUN , SHIN HYUN SUB , LEE SUNG WON , LEE HYUNG EUI , SEO YEONG UK , RYU SUNG WUK , LEE HYUK SOO
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L21/4832 , H01L23/49503 , H01L23/49513 , H01L23/49541 , H01L23/49568 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/95 , H01L2224/32057 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/73265 , H01L2224/83385 , H01L2224/85001 , H01L2224/85411 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85457 , H01L2224/85464 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15153 , H01L2924/15165 , H01L2924/157 , H01L2924/181 , H01L2924/19043 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： The present invention relates to structure and manufacture method for multi-row lead frame and semiconductor package, the method characterized by forming a pad portion on a metal material (first step); performing a surface plating process or organic material coating following the first pattern formation (second step); forming a second pattern on the metal material (third step); and packaging a semiconductor chip following the second pattern formation (fourth step), whereby an under-cut phenomenon is minimized by applying a gradual etching.
摘要翻译：本发明涉及多排引线框架和半导体封装的结构和制造方法，其特征在于在金属材料上形成焊盘部分（第一步骤）; 在第一图案形成之后执行表面电镀工艺或有机材料涂层（第二步骤）; 在金属材料上形成第二图案（第三步骤）; 并且在第二图案形成之后封装半导体芯片（第四步骤），由此通过施加渐进蚀刻来最小化底切现象。

3. 发明申请

WO2012005435A1 MANUFACTURING METHOD OF CHIP PACKAGE AND CHIP PACKAGE MANUFACTURED USING THE SAME 审中-公开
标题翻译：芯片封装的制造方法和使用该芯片封装制造的芯片封装的制造方法
公开(公告)号：WO2012005435A1
公开(公告)日：2012-01-12
申请号：PCT/KR2011/002628
申请日：2011-04-13
申请人： LG INNOTEK CO., LTD. , LEE, Hyung Eui , PARK, Chung Sik , CHUN, Hyun A , EOM, Sai Ran
发明人： LEE, Hyung Eui , PARK, Chung Sik , CHUN, Hyun A , EOM, Sai Ran
IPC分类号： H01L23/48 , H01L23/043
CPC分类号： H01L21/4832 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48664 , H01L2224/48839 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/48864 , H01L2224/83 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2224/92 , H01L2224/92247 , H01L2924/01014 , H01L2924/01028 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/15156 , H01L2924/157 , H01L2924/181 , H01L2924/00014 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： The present invention relates to a manufacturing method of a chip package, the method comprising: forming first leads and second leads, both having conductivity, on the top and bottom surfaces of a metal substrate; half-etching the top surface of the metal substrate to form a lead portion under the first leads and to form a die pad portion whose bottom is connected to the lead portion; attaching a chip onto the die pad portion and electrically connecting the chip and the first leads by a connector; forming an insulative molding portion on the metal substrate to bury the chip and the connector; and etching the bottom of the metal substrate to short-circuit the lead portion and the die pad portion, and a chip package manufactured using the same. Accordingly, the distance between a chip and first leads can be reduced by forming a conventional bump-shaped I/O pad in a lead shape, thus lead to cost reduction. Moreover, a large number of signal transmission systems can be reliably realized in a micro-pattern due to the lead shape. Moreover, the stability of the product can be improved by treating the thickness of the lead portion in the final step of the process.
摘要翻译：本发明涉及一种芯片封装的制造方法，所述方法包括：在金属基板的顶表面和底表面上形成具有导电性的第一引线和第二引线; 半蚀刻所述金属衬底的顶表面以在所述第一引线下方形成引线部分并形成其底部连接到所述引线部分的管芯焊盘部分; 将芯片附接到管芯焊盘部分上并通过连接器电连接芯片和第一引线; 在金属基板上形成绝缘模制部分以掩埋芯片和连接器; 以及蚀刻金属基板的底部以使引线部分和管芯焊盘部分短路，以及使用其制造的芯片封装。因此，通过形成引脚形状的常规凸起形I / O焊盘，可以减小芯片与第一引线之间的距离，从而导致成本降低。而且，由于引线形状，大量的信号传输系统能够可靠地以微图案实现。而且，通过在该工艺的最后步骤中处理引线部分的厚度可以改善产品的稳定性。

4. 发明申请

WO2010036051A3 STRUCTURE AND MANUFACTURE METHOD FOR MULTI-ROW LEAD FRAME AND SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：WO2010036051A3
公开(公告)日：2010-04-01
申请号：PCT/KR2009/005481
申请日：2009-09-25
申请人： LG INNOTEK CO., LTD. , KIM, Ji Yun , SHIN, Hyun Sub , LEE, Sung Won , LEE, Hyung Eui , SEO, Yeong Uk , RYU, Sung Wuk , LEE, Hyuk Soo
发明人： KIM, Ji Yun , SHIN, Hyun Sub , LEE, Sung Won , LEE, Hyung Eui , SEO, Yeong Uk , RYU, Sung Wuk , LEE, Hyuk Soo
IPC分类号： H01L23/495 , H01L21/60
摘要： The present invention relates to structure and manufacture method for multi-row lead frame and semiconductor package, the method characterized by forming a pad portion on a metal material (first step); performing a surface plating process or organic material coating following the first pattern formation (second step); forming a second pattern on the metal material (third step); and packaging a semiconductor chip following the second pattern formation (fourth step), whereby an under-cut phenomenon is minimized by applying a gradual etching.

5. 发明申请

WO2011059205A3 LEAD FRAME AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：铅框架及其制造方法
公开(公告)号：WO2011059205A3
公开(公告)日：2011-05-19
申请号：PCT/KR2010/007783
申请日：2010-11-05
申请人： LG INNOTEK CO., LTD. , EOM, Sai Ran , CHUN, Hyun A , PARK, Chung Sik , LEE, Hyung Eui
发明人： EOM, Sai Ran , CHUN, Hyun A , PARK, Chung Sik , LEE, Hyung Eui
IPC分类号： H01L23/495 , H01L21/60
摘要： An aspect of the present invention provides a lead frame, comprising lead portions each composed of a vertical portion and a horizontal portion, a die pad portion disconnected from the lead portions by support portions made of an insulating material, inner leads disposed to neighbor the die pad portion and formed on a top surface of the horizontal portions of the lead portions, and outer leads formed on a bottom surface of the vertical portions of the lead portions. In accordance with the present invention, a lead frame having a reduced wire length due to a fine circuit pattern, enabling flipchip bonding due to routability, and improving adhesive strength upon soldering due to a swell structure can be fabricated. Further, a warpage phenomenon in a manufacturing process can be prevented.
摘要翻译：本发明的一个方面提供了一种引线框架，其包括：引线部分，每个引线部分由垂直部分和水平部分组成;管芯焊盘部分，其由引线部分通过由绝缘材料制成的支撑部分内部引线，其被布置为与管芯焊盘部分相邻并形成在引线部分的水平部分的顶表面上;以及外部引线，其形成在引线部分的垂直部分的底表面上。根据本发明，可以制造由于精细电路图案而导致线长减小的引线框架，由于可布线性而使倒装芯片键合，并且由于膨胀结构而提高焊接时的粘合强度。此外，可以防止制造过程中的翘曲现象。

6. 发明申请

WO2012005435A9 MANUFACTURING METHOD OF CHIP PACKAGE AND CHIP PACKAGE MANUFACTURED USING THE SAME 审中-公开
标题翻译：使用其制造的芯片封装和芯片封装的制造方法
公开(公告)号：WO2012005435A9
公开(公告)日：2012-02-16
申请号：PCT/KR2011002628
申请日：2011-04-13
申请人： LG INNOTEK CO LTD , LEE HYUNG EUI , PARK CHUNG SIK , CHUN HYUN A , EOM SAI RAN
发明人： LEE HYUNG EUI , PARK CHUNG SIK , CHUN HYUN A , EOM SAI RAN
IPC分类号： H01L23/48 , H01L23/043
CPC分类号： H01L21/4832 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48664 , H01L2224/48839 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/48864 , H01L2224/83 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2224/92 , H01L2224/92247 , H01L2924/01014 , H01L2924/01028 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/15156 , H01L2924/157 , H01L2924/181 , H01L2924/00014 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： The present invention relates to a manufacturing method of a chip package, the method comprising: forming first leads and second leads, both having conductivity, on the top and bottom surfaces of a metal substrate; half-etching the top surface of the metal substrate to form a lead portion under the first leads and to form a die pad portion whose bottom is connected to the lead portion; attaching a chip onto the die pad portion and electrically connecting the chip and the first leads by a connector; forming an insulative molding portion on the metal substrate to bury the chip and the connector; and etching the bottom of the metal substrate to short-circuit the lead portion and the die pad portion, and a chip package manufactured using the same. Accordingly, the distance between a chip and first leads can be reduced by forming a conventional bump-shaped I/O pad in a lead shape, thus lead to cost reduction. Moreover, a large number of signal transmission systems can be reliably realized in a micro-pattern due to the lead shape. Moreover, the stability of the product can be improved by treating the thickness of the lead portion in the final step of the process.
摘要翻译：本发明涉及一种芯片封装的制造方法，该方法包括：在金属基板的顶表面和底表面上形成具有导电性的第一引线和第二引线; 半蚀刻金属基板的顶表面，以在第一引线下方形成引线部分并形成其底部连接到引线部分的芯片焊盘部分; 将芯片附接到芯片焊盘部分上并通过连接器电连接芯片和第一引线; 在所述金属基板上形成绝缘成型部，以埋设所述芯片和所述连接器; 并且蚀刻金属基板的底部以使引线部分和芯片焊盘部分短路，以及使用其形成的芯片封装。因此，可以通过形成引线形状的传统的凸起形状的I / O焊盘来减小芯片与第一引线之间的距离，从而降低成本。此外，由于引线形状，可以以微图案可靠地实现大量的信号传输系统。此外，通过在该方法的最后步骤中处理引线部分的厚度可以提高产品的稳定性。

7. 发明申请

WO2011059205A2 LEAD FRAME AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：铅框架及其制造方法
公开(公告)号：WO2011059205A2
公开(公告)日：2011-05-19
申请号：PCT/KR2010007783
申请日：2010-11-05
申请人： LG INNOTEK CO LTD , EOM SAI RAN , CHUN HYUN A , PARK CHUNG SIK , LEE HYUNG EUI
发明人： EOM SAI RAN , CHUN HYUN A , PARK CHUNG SIK , LEE HYUNG EUI
CPC分类号： H01L23/49861 , H01L21/486 , H01L23/3121 , H01L24/48 , H01L24/49 , H01L2224/48011 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01082 , H01L2924/014 , H01L2924/15153 , H01L2924/15165 , H01L2924/15747 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： An aspect of the present invention provides a lead frame, comprising lead portions each composed of a vertical portion and a horizontal portion, a die pad portion disconnected from the lead portions by support portions made of an insulating material, inner leads disposed to neighbor the die pad portion and formed on a top surface of the horizontal portions of the lead portions, and outer leads formed on a bottom surface of the vertical portions of the lead portions. In accordance with the present invention, a lead frame having a reduced wire length due to a fine circuit pattern, enabling flipchip bonding due to routability, and improving adhesive strength upon soldering due to a swell structure can be fabricated. Further, a warpage phenomenon in a manufacturing process can be prevented.
摘要翻译：本发明的一个方面提供了一种引线框架，其包括由垂直部分和水平部分构成的引线部分，通过由绝缘材料制成的支撑部分与引线部分断开的管芯焊盘部分，设置成邻近管芯的内部引线并且形成在引线部分的水平部分的顶表面上，以及形成在引线部分的垂直部分的底表面上的外引线。根据本发明，可以制造由于精细电路图形而具有减少的线长的引线框架，由于可布线性而实现倒装芯片接合，并且可以提高由于膨胀结构而导致的焊接时的粘合强度。此外，可以防止制造过程中的翘曲现象。

8. 发明申请

WO2011055984A2 LEADFRAME AND METHOD OF MANUFACURING THE SAME 审中-公开
标题翻译： LEADFRAME及其制造方法
公开(公告)号：WO2011055984A2
公开(公告)日：2011-05-12
申请号：PCT/KR2010007730
申请日：2010-11-04
申请人： LG INNOTEK CO LTD , CHUN HYUN A , PARK CHUNG SIK , EOM SAI RAN , LEE HYUNG EUI
发明人： CHUN HYUN A , PARK CHUNG SIK , EOM SAI RAN , LEE HYUNG EUI
IPC分类号： H01L23/495 , H01L23/498
CPC分类号： H01L21/4828 , H01L23/495 , H01L23/49558 , H01L24/48 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a leadframe and a method for manufacturing the same. The leadframe includes a lead unit having vertical and horizontal parts, a die pad unit separated from the lead unit by an support unit formed of insulating material, an inner lead formed adjacent to the die pad unit and on the horizontal part of the lead unit, and an outer lead formed on a bottom surface of the vertical part of the lead unit. Such a structure of the leadframe shortens a wire length, allows flip chip bonding, and improves soldering adhesive. The structure of the leadframe enhances physical strength thereof by enhancing a support force of an insulator. Moreover, the leadframe includes a fine plating pattern having a small plating deviation and a superior structure, and has excellent durability and improved thermal conduction by entirely plating surfaces of the die pad.
摘要翻译：引线框架及其制造方法技术领域本发明涉及一种引线框架及其制造方法。引线框架包括具有垂直和水平部分的引线单元，通过由绝缘材料形成的支撑单元与引线单元分离的管芯焊盘单元，邻近管芯焊盘单元和引线单元的水平部分形成的内部引线，以及形成在引线单元的垂直部分的底表面上的外部引线。引线框架的这种结构缩短了导线长度，允许倒装芯片结合，并改善了焊接粘合剂。引线框架的结构通过增强绝缘体的支撑力来提高其物理强度。此外，引线框架包括具有小电镀偏差和优良结构的精细电镀图案，并且通过整个电镀芯片焊盘的表面而具有优异的耐久性和改善的热传导。

9. 发明申请

WO2010137899A3 LEADFRAME AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：WO2010137899A3
公开(公告)日：2010-12-02
申请号：PCT/KR2010/003384
申请日：2010-05-27
申请人： LG INNOTEK CO., LTD. , EOM, Sai Ran , LEE, Hyung Eui , PARK, Chung Sik , CHUN, Hyun A. , YOON, Hye Sun
发明人： EOM, Sai Ran , LEE, Hyung Eui , PARK, Chung Sik , CHUN, Hyun A. , YOON, Hye Sun
IPC分类号： H01L23/495 , H01L21/60
摘要： Disclosed is a leadframe. The leadframe comprises a die pad part, at least one lead part, and at least one supporting part. A semiconductor chip is mounted on a first surface of the leadframe at the die pad. The at least one lead part electrically connects the semiconductor chip to at least one external circuit. The at least one supporting part is adjacent to a second surface opposited the first surface, includes an insulating material, and insulates the at least one lead part from each other.

10. 发明申请

WO2011055984A3 LEADFRAME AND METHOD OF MANUFACURING THE SAME 审中-公开
公开(公告)号：WO2011055984A3
公开(公告)日：2011-05-12
申请号：PCT/KR2010/007730
申请日：2010-11-04
申请人： LG INNOTEK CO., LTD. , CHUN, Hyun, A , PARK, Chung Sik , EOM, Sai Ran , LEE, Hyung Eui
发明人： CHUN, Hyun, A , PARK, Chung Sik , EOM, Sai Ran , LEE, Hyung Eui
IPC分类号： H01L23/495 , H01L23/498
摘要： The present invention relates to a leadframe and a method for manufacturing the same. The leadframe includes a lead unit having vertical and horizontal parts, a die pad unit separated from the lead unit by an support unit formed of insulating material, an inner lead formed adjacent to the die pad unit and on the horizontal part of the lead unit, and an outer lead formed on a bottom surface of the vertical part of the lead unit. Such a structure of the leadframe shortens a wire length, allows flip chip bonding, and improves soldering adhesive. The structure of the leadframe enhances physical strength thereof by enhancing a support force of an insulator. Moreover, the leadframe includes a fine plating pattern having a small plating deviation and a superior structure, and has excellent durability and improved thermal conduction by entirely plating surfaces of the die pad.

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