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    • 3. 发明申请
    • PROCESSOR HARDWARE PIPELINE CONFIGURED FOR SINGLE INSTRUCTION ADDRESS EXTRACTION AND MEMORY ACCESS OPERATION
    • 处理器硬件管道配置为单指令地址提取和存储器访问操作
    • WO2013049759A1
    • 2013-04-04
    • PCT/US2012/058174
    • 2012-09-30
    • QUALCOMM INCORPORATEDDE, Subrato K.MORROW, Michael WilliamKHAN, Moinul H.BAPST, Mark
    • DE, Subrato K.MORROW, Michael WilliamKHAN, Moinul H.BAPST, Mark
    • G06F9/30
    • G06F9/30043
    • Memory access instructions, such as load and store instructions, are processed in a processor-based system. Processor hardware pipeline configurations enable efficient performance of memory access instructions, such as a pipeline configuration that enables, for a memory access operation request by a register-operand based virtual machine, computation of the memory location corresponding to a virtual-machine register by extracting a bit-field from the virtual-machine instruction and accessing (load or store) the computed memory location that represents a virtual register of the virtual-machine, in a single pass through the pipeline. Thus this processor hardware pipeline configuration enables a virtual machine register read/write operation to be performed by a single hardware processor instruction through a single pass in the processor hardware pipeline, for a register-operand based virtual machine.
    • 诸如加载和存储指令之类的存储器访问指令在基于处理器的系统中被处理。 处理器硬件流水线配置能够有效地执行存储器访问指令,例如流水线配置,其能够通过基于寄存器操作数的虚拟机对存储器访问操作请求进行与虚拟机寄存器对应的存储器位置的计算, 来自虚拟机指令的位字段,并且在通过管道的单次通过中访问(加载或存储)表示虚拟机的虚拟寄存器的计算的存储器位置。 因此,这种处理器硬件流水线配置使得能够通过单个硬件处理器指令通过处理器硬件流水线中的单次执行对基于寄存器操作数的虚拟机执行虚拟机寄存器读/写操作。