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1. 发明申请

WO0201382A3 METHOD AND APPARATUS FOR PROVIDING REAL-TIME OPERATION IN A PERSONAL COMPUTER SYSTEM 审中-公开
标题翻译：用于在个人计算机系统中提供实时操作的方法和装置
公开(公告)号：WO0201382A3
公开(公告)日：2003-07-24
申请号：PCT/US0118384
申请日：2001-06-07
申请人： INTEL CORP , KARDACH JAMES
发明人： KARDACH JAMES
IPC分类号： G06F15/78
CPC分类号： G06F15/7864
摘要： According to one embodiment, a computer system is disclosed. The computer system comprises a central processing unit (CPU) and a non-symmetric processor (NSP) coupled to the CPU. The NSP is integrated on the same semiconductor die as the CPU.
摘要翻译：根据一个实施例，公开了一种计算机系统。计算机系统包括中央处理单元（CPU）和耦合到CPU的非对称处理器（NSP）。 NSP集成在与CPU相同的半导体裸片上。

2. 发明申请

WO2006039204A3 A METHOD AND APPARATUS FOR POLARIZING ELECTROMAGNETIC RADIATION 审中-公开
公开(公告)号：WO2006039204A3
公开(公告)日：2006-04-13
申请号：PCT/US2005/034157
申请日：2005-09-21
申请人： INTEL CORPORATION , WILLIAMS, David , KARDACH, James , GOLDSTEIN, Michael
发明人： WILLIAMS, David , KARDACH, James , GOLDSTEIN, Michael
IPC分类号： G02B27/28 , G03F7/20 , G02F1/09
摘要： A method and apparatus for polarizing electromagnetic radiation is provided. The electromagnetic radiation may be divided into first and second portions, substantially all of the first portion may be linearly polarized in a first direction and substantially all of the second portion may be linearly polarized in a second direction, the first direction being substantially orthogonal to the second direction. The linear polarization of at least one of the first and second portions may be changed such that substantially all of both of the first and second portions are linearly polarized in a third direction. At least one of the first and second portions may be redirected such that substantially all of both the first and second portions are propagating in a fourth direction.

3. 发明申请

WO0201348A3 METHOD AND APPARATUS FOR PROVIDING REAL-TIME OPERATION IN A PERSONAL COMPUTER SYSTEM 审中-公开
标题翻译：用于在个人计算机系统中提供实时操作的方法和装置
公开(公告)号：WO0201348A3
公开(公告)日：2003-05-22
申请号：PCT/US0118679
申请日：2001-06-07
申请人： INTEL CORP , KARDACH JAMES
发明人： KARDACH JAMES
IPC分类号： G06F9/48 , G06F9/54 , G06F13/26
CPC分类号： G06F9/4881
摘要： A method is disclosed. The method includes receiving real-time data at a personal computer implementing a general purpose operating system, generating a real-time event at the personal computer and determining whether the real-time event has a higher priority than a first event being processed at the personal computer. If the real-time event has a higher priority than the first event being processed, the real-time event is processed.
摘要翻译：公开了一种方法。该方法包括在实现通用操作系统的个人计算机上接收实时数据，在个人计算机上产生实时事件并确定实时事件是否具有比正在个人处理的第一事件更高的优先级电脑。如果实时事件的优先级高于正在处理的第一个事件，则处理实时事件。

4. 发明申请

WO1997024653A1 POWER MANAGEMENT APPARATUS AND METHOD 审中-公开
标题翻译：电力管理装置和方法
公开(公告)号：WO1997024653A1
公开(公告)日：1997-07-10
申请号：PCT/US1996020807
申请日：1996-12-27
申请人： INTEL CORPORATION , KARDACH, James, P. , CHUNG, Chih-Hung , ZILLER, Jason
发明人： INTEL CORPORATION
IPC分类号： G06F01/32
CPC分类号： G06F1/3215 , G06F1/3237 , G06F1/3275 , Y02D10/128 , Y02D10/14
摘要： A computer system is provided for monitoring the activity of a bus controller (208) of a processor (204) and responsive thereto for controlling the power consumption of a target controller such as memory controller (216) coupled to the bus controller (208). The computer system includes a bus (202), a processor (204), and a bus activity monitor (212) for generating a bus activity signal indicative of activity in the bus controller (208). The target controller (memory controller (216)) controls the exchange of information between the processor (204) and a target circuit such as DRAM (218). The target controller (216) has an input (215) for receiving a sequencing signal. The computer system additionally includes a power management circuit (220) for controlling the power consumption of the target controller (216). The power management circuit (220) receives the bus activity signal and generates the sequencing signal in response to the bus activity signal.
摘要翻译：提供了一种计算机系统，用于监视处理器（204）的总线控制器（208）的活动，并响应于此控制用于控制诸如耦合到总线控制器（208）的存储器控制器（216）的目标控制器的功耗。计算机系统包括总线（202），处理器（204）和总线活动监视器（212），用于产生指示总线控制器（208）中的活动的总线活动信号。目标控制器（存储器控制器（216））控制处理器（204）和诸如DRAM（218）的目标电路之间的信息交换。目标控制器（216）具有用于接收排序信号的输入端（215）。计算机系统还包括用于控制目标控制器（216）的功耗的电源管理电路（220）。功率管理电路（220）响应于总线活动信号接收总线活动信号并产生排序信号。

5. 发明申请

WO2014105172A1 POWER CONSERVATION BASED ON HARD DISK ROTATIONAL INERTIA 审中-公开
标题翻译：基于硬盘旋转运算的功率保护
公开(公告)号：WO2014105172A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/047639
申请日：2013-06-25
申请人： INTEL CORPORATION , KARDACH, James P. , MACDONALD, Kirsty , GIBSON, Peter
发明人： KARDACH, James P. , MACDONALD, Kirsty , GIBSON, Peter
IPC分类号： G11B19/28
CPC分类号： G11B19/28
摘要： Various embodiments are generally directed recurringly cycling the driving of a platter media of a hard drive with a motor, allowing rotation of the platter media to slow only to a threshold rotational speed to balance power conservation with delays in accessing data. A method comprises driving platter media of a hard drive to rotate at a selected normal rotational speed, retrieving data stored on the platter media when the platter media rotates at the normal rotational speed, ceasing to drive the platter media to rotate to allow the platter media to rotate under rotational inertia imparted to the platter media, monitoring a current rotational speed of the platter media, and resuming driving the platter media to rotate based on the current rotational speed falling to a lower threshold rotational speed selected to be less than the normal rotational speed. Other embodiments are described and claimed.
摘要翻译：各种实施例通常定期循环利用电动机驱动硬盘驱动器的盘片介质，允许盘片介质的旋转仅减慢到阈值旋转速度以平衡功率节省与访问数据的延迟。一种方法包括驱动硬盘驱动器的盘式介质以选定的正常转速旋转，当盘式介质以正常转速旋转时检索存储在盘片介质上的数据，停止驱动盘式介质旋转以允许盘片介质在旋转惯性下旋转到盘片介质上，监测盘片介质的当前旋转速度，并且基于当前旋转速度下降到低于正常旋转的较低阈值旋转速度，重新开始驱动盘片介质旋转速度。描述和要求保护其他实施例。

6. 发明申请

WO2006130763A3 PARTIAL PAGE SCHEME FOR MEMORY TECHNOLOGIES 审中-公开
公开(公告)号：WO2006130763A3
公开(公告)日：2006-12-07
申请号：PCT/US2006/021271
申请日：2006-05-31
申请人： INTEL CORPORATION , JAIN, Sandeep , MISHRA, Animesh , KARDACH, James
发明人： JAIN, Sandeep , MISHRA, Animesh , KARDACH, James
IPC分类号： G11C7/10 , G11C8/12 , G06F12/00
摘要： Systems and methods of managing memory provide for detecting a request to activate a memory portion that is limited in size to a partial page size, where the partial page size is less than a full page size associated with the memory. In one embodiment, detecting the request may include identifying a row address and partial page address associated with the request, where the partial page address indicates that the memory portion is to be limited to the partial page size.

7. 发明申请

WO2006130763A2 PARTIAL PAGE SCHEME FOR MEMORY TECHNOLOGIES 审中-公开
标题翻译：内存技术的部分页面方案
公开(公告)号：WO2006130763A2
公开(公告)日：2006-12-07
申请号：PCT/US2006021271
申请日：2006-05-31
申请人： INTEL CORP , JAIN SANDEEP , MISHRA ANIMESH , KARDACH JAMES
发明人： JAIN SANDEEP , MISHRA ANIMESH , KARDACH JAMES
IPC分类号： G11C7/10 , G06F12/00 , G11C8/12
CPC分类号： G11C7/1021 , G11C7/1045 , G11C8/12
摘要： Systems and methods of managing memory provide for detecting a request to activate a memory portion that is limited in size to a partial page size, where the partial page size is less than a full page size associated with the memory. In one embodiment, detecting the request may include identifying a row address and partial page address associated with the request, where the partial page address indicates that the memory portion is to be limited to the partial page size.
摘要翻译：管理存储器的系统和方法提供用于检测激活被限制在局部页面大小的部分页面大小的存储器部分的请求，其中部分页面大小小于与存储器相关联的整个页面大小。在一个实施例中，检测请求可以包括识别与该请求相关联的行地址和部分页面地址，其中部分页面地址指示存储器部分被限制为部分页面大小。

8. 发明申请

WO2007002921A3 DISPLAY CONTROLLER 审中-公开
公开(公告)号：WO2007002921A3
公开(公告)日：2007-01-04
申请号：PCT/US2006/025774
申请日：2006-06-29
申请人： INTEL CORPORATION , KARDACH, James P. , WILLIAMS, David , BHOWMIK, Achintya K. , COOPER, Barnes
发明人： KARDACH, James P. , WILLIAMS, David , BHOWMIK, Achintya K. , COOPER, Barnes
IPC分类号： G09G3/20
摘要： Apparatus and systems, as well as methods and articles, may operate to update video display pixels. A video display bus can communicate data to a video display according to specified clock frequencies and a refresh time period. Power conservation can be enhanced by adjusting the specified clock frequencies and/or refresh time period to provide idle time on the video display bus.

9. 发明申请

WO2007002921A2 DISPLAY CONTROLLER 审中-公开
标题翻译：显示控制器
公开(公告)号：WO2007002921A2
公开(公告)日：2007-01-04
申请号：PCT/US2006025774
申请日：2006-06-29
申请人： INTEL CORP , KARDACH JAMES P , WILLIAMS DAVID , BHOWMIK ACHINTYA K , COOPER BARNES
发明人： KARDACH JAMES P , WILLIAMS DAVID , BHOWMIK ACHINTYA K , COOPER BARNES
IPC分类号： G09G3/36 , G09G5/36
CPC分类号： G09G5/006 , G09G3/3648 , G09G5/363 , G09G2330/021 , G09G2340/0435
摘要： Apparatus and systems, as well as methods and articles, may operate to update video display pixels. A video display bus can communicate data to a video display according to specified clock frequencies and a refresh time period. Power conservation can be enhanced by adjusting the specified clock frequencies and/or refresh time period to provide idle time on the video display bus.
摘要翻译：设备和系统以及方法和物品可以操作来更新视频显示像素。视频显示总线可以根据指定的时钟频率和刷新时间周期将数据传送到视频显示器。可以通过调整指定的时钟频率和/或刷新时间来提高功率节省，从而在视频显示总线上提供空闲时间。

10. 发明申请

WO2007002901A1 REDUCTION OF SNOOP ACCESSES 审中-公开
标题翻译：减少SNOOP接入
公开(公告)号：WO2007002901A1
公开(公告)日：2007-01-04
申请号：PCT/US2006/025621
申请日：2006-06-29
申请人： INTEL CORPORATION , KARDACH, James , WILLIAMS, David
发明人： KARDACH, James , WILLIAMS, David
IPC分类号： G06F12/08
CPC分类号： G06F12/0835 , G06F12/0804 , Y02D10/13
摘要： Techniques that may be utilized in reduction of snoop accesses are described. In one embodiment, a method includes receiving a page snoop command that identifies a page address corresponding to a memory access request by an input/output (I/O) device. One or more cache lines that match the page address may be evicted. Furthermore, memory access by a processor core may be monitored to determine whether the processor core memory access is within the page address.
摘要翻译：描述了可以用于减少窥探访问的技术。在一个实施例中，一种方法包括接收通过输入/输出（I / O）设备识别对应于存储器访问请求的页面地址的页面窥探命令。与页面地址匹配的一个或多个高速缓存行可能被移除。此外，可以监视处理器核心的存储器访问以确定处理器核心存储器访问是否在页面地址内。

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