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1. 发明申请

WO2006059283A3 STREAMING MEMORY CONTROLLER 审中-公开
公开(公告)号：WO2006059283A3
公开(公告)日：2006-06-08
申请号：PCT/IB2005/053970
申请日：2005-11-30
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BURCHARD, Artur , HEKSTRA-NOWACKA, Ewa , HARMSZE, Francoise, J. , VAN DEN HAMER, Peter
发明人： BURCHARD, Artur , HEKSTRA-NOWACKA, Ewa , HARMSZE, Francoise, J. , VAN DEN HAMER, Peter
IPC分类号： H04L12/56
摘要： A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N). The memory controller (SMC) comprises a first interface (PI), a streaming memory unit (SMU) and a second interface (MI). The first interface (PI) is used for connecting the memory controller (SMC) to the network (N) for receiving and transmitting data streams (STl - ST4). The streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (STl - ST4) between the network (N) and the memory (MEM). The streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (STl - ST4) and a buffer managing unit (BMU) for managing the temporarily storing of the data streams (STl - ST4) in the buffer (B). The second interlace (MI) is coupled to the streaming memory unit (SMU) for connecting the memory controller (SMC) to the memory (MEM) in order to exchange data with the memory (MEM) in bursts. The streaming memory unit (SMU) is provided to implement network services of the network (N) onto the memory (MEM).

2. 发明申请

WO2005088468A3 INTEGRATED CIRCUIT AND METHOD FOR MEMORY ACCESS CONTROL 审中-公开
公开(公告)号：WO2005088468A3
公开(公告)日：2005-09-22
申请号：PCT/IB2005/050816
申请日：2005-03-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BURCHARD, Artur, T. , HARMSZE, Francoise, J.
发明人： BURCHARD, Artur, T. , HARMSZE, Francoise, J.
IPC分类号： G06F13/14 , G06F13/16
摘要： An integrated circuit comprising at least one processing module (PROC) for processing an application (APL) requiring specific communication parameter, at least one dynamic random access memory means (MM) for storing data, wherein the memory means (MM) is operable by a plurality of predefined operating modes, is provided. Additionally, at least one memory access selection means (SM) for selecting one of said plurality of predefined operating modes based on said communication parameters and at least one memory controller (MC) for controlling the access of said at least one dynamic random access memory means (MM) according to said predefined operating modes selected by said memory access selecting means (SM) is provided. Each of said memory controller (MC) are associated to one of the dynamic random access means (MM). An interconnect means (IM) couples the processing modules (PROC) and the memory controller (MC), such that the communication over the interconnect means (IM) is achieved.

3. 发明申请

WO2006059283A2 STREAMING MEMORY CONTROLLER 审中-公开
标题翻译：流控记忆体控制器
公开(公告)号：WO2006059283A2
公开(公告)日：2006-06-08
申请号：PCT/IB2005053970
申请日：2005-11-30
申请人： KONINKL PHILIPS ELECTRONICS NV , BURCHARD ARTUR , HEKSTRA-NOWACKA EWA , HARMSZE FRANCOISE J , VAN DEN HAMER PETER
发明人： BURCHARD ARTUR , HEKSTRA-NOWACKA EWA , HARMSZE FRANCOISE J , VAN DEN HAMER PETER
CPC分类号： H04L49/9063 , G06F13/1673 , H04L49/90
摘要： A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N). The memory controller (SMC) comprises a first interface (PI), a streaming memory unit (SMU) and a second interface (MI). The first interface (PI) is used for connecting the memory controller (SMC) to the network (N) for receiving and transmitting data streams (STl - ST4). The streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (STl - ST4) between the network (N) and the memory (MEM). The streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (STl - ST4) and a buffer managing unit (BMU) for managing the temporarily storing of the data streams (STl - ST4) in the buffer (B). The second interlace (MI) is coupled to the streaming memory unit (SMU) for connecting the memory controller (SMC) to the memory (MEM) in order to exchange data with the memory (MEM) in bursts. The streaming memory unit (SMU) is provided to implement network services of the network (N) onto the memory (MEM).
摘要翻译：提供存储器控制器（SMC）用于将存储器（MEM）耦合到网络（N）。存储器控制器（SMC）包括第一接口（PI），流存储器单元（SMU）和第二接口（MI）。第一接口（PI）用于将存储器控制器（SMC）连接到网络（N），用于接收和发送数据流（ST1-ST4）。流存储器单元（SMU）耦合到第一接口（PI），用于控制网络（N）和存储器（MEM）之间的数据流（ST1-ST4）。流存储器单元（SMU）包括用于临时存储至少部分数据流（ST1-ST4）的缓冲器（B）和用于管理数据流（ST1-ST4）的临时存储的缓冲器管理单元（BMU）在缓冲器（B）中。第二交错（MI）耦合到流存储器单元（SMU），用于将存储器控制器（SMC）连接到存储器（MEM），以便以突发方式与存储器（MEM）交换数据。提供流式存储器单元（SMU）以将网络（N）的网络服务实现到存储器（MEM）上。

4. 发明申请

WO2005088468A2 INTEGRATED CIRCUIT AND METHOD FOR MEMORY ACCESS CONTROL 审中-公开
标题翻译：集成电路和存储器访问控制方法
公开(公告)号：WO2005088468A2
公开(公告)日：2005-09-22
申请号：PCT/IB2005050816
申请日：2005-03-04
申请人： KONINKL PHILIPS ELECTRONICS NV , BURCHARD ARTUR T , HARMSZE FRANCOISE J
发明人： BURCHARD ARTUR T , HARMSZE FRANCOISE J
IPC分类号： G06F13/14 , G06F13/16
CPC分类号： G06F13/1694 , Y02D10/14
摘要： An integrated circuit comprising at least one processing module (PROC) for processing an application (APL) requiring specific communication parameter, at least one dynamic random access memory means (MM) for storing data, wherein the memory means (MM) is operable by a plurality of predefined operating modes, is provided. Additionally, at least one memory access selection means (SM) for selecting one of said plurality of predefined operating modes based on said communication parameters and at least one memory controller (MC) for controlling the access of said at least one dynamic random access memory means (MM) according to said predefined operating modes selected by said memory access selecting means (SM) is provided. Each of said memory controller (MC) are associated to one of the dynamic random access means (MM). An interconnect means (IM) couples the processing modules (PROC) and the memory controller (MC), such that the communication over the interconnect means (IM) is achieved.
摘要翻译：一种集成电路，包括用于处理需要特定通信参数的应用（APL）的至少一个处理模块（PROC），用于存储数据的至少一个动态随机存取存储器装置（MM），其中存储装置（MM）可由提供了多种预定义的操作模式。另外，至少一个用于基于所述通信参数选择所述多个预定操作模式之一的存储器访问选择装置（SM）以及用于控制所述至少一个动态随机存取存储器装置的访问的至少一个存储器控制器（MC）（MM）根据由所述存储器访问选择装置（SM）选择的所述预定义的操作模式提供。所述存储器控制器（MC）中的每一个与动态随机存取装置（MM）之一相关联。互连装置（IM）耦合处理模块（PROC）和存储器控制器（MC），从而实现通过互连装置（IM）的通信。

5. 发明申请

WO2005010781A1 AN OBJECT CREATION STRATEGY FOR SIMULATOR MODULES 审中-公开
标题翻译：模拟器模块的对象创建策略
公开(公告)号：WO2005010781A1
公开(公告)日：2005-02-03
申请号：PCT/IB2004/051221
申请日：2004-07-14
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , KENTER, Harm, J., H., N. , HARMSZE, Francoise, J. , BURCHARD, Artur, T.
发明人： KENTER, Harm, J., H., N. , HARMSZE, Francoise, J. , BURCHARD, Artur, T.
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： The present invention relates to a method of performing a simulation based on a simulation model, wherein the simulation model comprises a number of interconnected simulation objects, where at least part of the simulation objects is adapted to be sim+ted based on simulation code defined in accessible modules identified by a module ID, and where at least a part of said accessible modules has an attached module specific object creator defining how the simulation code in the module is to be handled when simulating an object defined by the module, the method of performing the simulation comprising the steps of: initializing the simulation by registering, in a simulation system accessible d ' abase, a link between the module ID and how to access the module specific object creator and accessing said module specific object creator when simulating an object defined by the attached module. Thereby the definition on how the simulation code in the modules is to be handled is no longer inside the simulator, and the kernel of the simulator does not need to be recompiled when adding new modules. Instead, the simulator can just look in the database, which provides the link between the module names from the system model and how to access the module specific object creator.
摘要翻译：本发明涉及一种基于仿真模型执行仿真的方法，其中仿真模型包括多个互连的仿真对象，其中至少部分仿真对象适于基于模拟代码中的定义由模块ID识别的可访问模块，并且其中至少一部分所述可访问模块具有附加的模块特定对象创建者，其定义当模拟由模块定义的对象时模块中的模拟代码如何被处理，执行方法该模拟包括以下步骤：通过在模拟系统可访问的模拟系统中注册模块ID之间的链接以及如何访问模块特定对象创建者并且在模拟由附件模块。因此，如何处理模块中的模拟代码的定义不再在模拟器内，并且在添加新模块时，模拟器的内核不需要重新编译。相反，模拟器只能查看数据库，这提供了来自系统模型的模块名称之间的链接以及如何访问模块特定对象创建者。

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