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1. 发明申请

WO2018129166A1 NESTING FENDERS 审中-公开
公开(公告)号：WO2018129166A1
公开(公告)日：2018-07-12
申请号：PCT/US2018/012353
申请日：2018-01-04
申请人： DENNEY, John D., Jr. , CARRASCA, Robert , HAMLIN, Christopher
发明人： DENNEY, John D., Jr. , CARRASCA, Robert , HAMLIN, Christopher
IPC分类号： B63B59/02 , B63B21/00 , B63B43/18
CPC分类号： B63B59/02 , B63B2059/025 , B63C9/26 , E02B3/26
摘要： An arrangement of fenders nested together for compact storage, the fenders including two or more cylindrical bodies having a cavity accessed through the fender top, the fenders being similar shape but graduated in size such that the cavity of a larger fender tensionally receives the next smaller sized fender, the outer diameter of the smaller fender equal to the inner diameter of the larger fender cavity. A fender has a rigid inner core surrounded by a compressible shell made of foam or similar material. The inner core has attachment points for a rope or line. The smallest nesting fender in the set has a cavity diameter sized to fit a commercially-available, off-the-shelf fender. The fenders may be separated and deployed at individual locations on a vessel, or kept together and deployed as a single fender capable of absorbing a greater impact than any of the fenders individually would absorb.

2. 发明申请

WO2008039814A3 CIRCUIT AND METHOD FOR GENERATING ELECTRICAL SOLITONS WITH JUNCTION FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：用场效应晶体管生成电孤子的电路和方法
公开(公告)号：WO2008039814A3
公开(公告)日：2008-05-29
申请号：PCT/US2007079477
申请日：2007-09-26
申请人： DSM SOLUTIONS INC , HAMLIN CHRISTOPHER L
发明人： HAMLIN CHRISTOPHER L
IPC分类号： H03B5/18
CPC分类号： H03B5/18
摘要： A circuit can include an amplifier having at least a first junction field effect transistor (JFET) of a first conductivity type with a source coupled to a first power supply node, and a drain coupled to an amplifier output node. A first variable bias circuit can be coupled between the drain and at least one gate of the first JFET. The first variable bias circuit can alter a direct current (DC) bias to the first JFET according a potential at the amplifier output node. A first bias impedance can be coupled between the drain of the first JFET and a second power supply node. The circuit can also include a non-linear transmission line (NLTL) coupled between the amplifier output and a gate of the first JFET. The NLTL being configured to propagate an electrical soliton.
摘要翻译：电路可以包括放大器，该放大器具有第一导电类型的至少第一结型场效应晶体管（JFET），其源极耦合到第一电源节点，漏极耦合到放大器输出节点。第一可变偏置电路可以耦合在第一JFET的漏极和至少一个栅极之间。第一可变偏置电路可以根据放大器输出节点处的电位来改变到第一JFET的直流（DC）偏置。第一偏置阻抗可以耦合在第一JFET的漏极和第二电源节点之间。该电路还可以包括耦合在放大器输出和第一JFET的栅极之间的非线性传输线（NLTL）。 NLTL被配置为传播电孤子。

3. 发明申请

WO2008039814A2 CIRCUIT AND METHOD FOR GENERATING ELECTRICAL SOLITONS WITH JUNCTION FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：用于产生具有连接场效应晶体管的电极的电路和方法
公开(公告)号：WO2008039814A2
公开(公告)日：2008-04-03
申请号：PCT/US2007/079477
申请日：2007-09-26
申请人： DSM SOLUTIONS, INC. , HAMLIN, Christopher, L.
发明人： HAMLIN, Christopher, L.
IPC分类号： H03B5/12
CPC分类号： H03B5/18
摘要： A circuit can include an amplifier having at least a first junction field effect transistor (JFET) of a first conductivity type with a source coupled to a first power supply node, and a drain coupled to an amplifier output node. A first variable bias circuit can be coupled between the drain and at least one gate of the first JFET. The first variable bias circuit can alter a direct current (DC) bias to the first JFET according a potential at the amplifier output node. A first bias impedance can be coupled between the drain of the first JFET and a second power supply node. The circuit can also include a non-linear transmission line (NLTL) coupled between the amplifier output and a gate of the first JFET. The NLTL being configured to propagate an electrical soliton.
摘要翻译：电路可以包括具有至少第一导电类型的第一结场效应晶体管（JFET）的放大器，其中耦合到第一电源节点的源极和耦合到放大器输出节点的漏极。第一可变偏置电路可以耦合在第一JFET的漏极和至少一个栅极之间。第一可变偏置电路可以根据放大器输出节点处的电位改变到第一JFET的直流（DC）偏置。第一偏置阻抗可以耦合在第一JFET的漏极和第二电源节点之间。电路还可以包括耦合在放大器输出和第一JFET的栅极之间的非线性传输线（NLTL）。 NLTL被配置为传播电孤子。

4. 发明申请

WO2009079244A1 SYSTEM AND METHOD FOR ROUTING CONNECTIONS 审中-公开
标题翻译：用于路由连接的系统和方法
公开(公告)号：WO2009079244A1
公开(公告)日：2009-06-25
申请号：PCT/US2008/085782
申请日：2008-12-08
申请人： DSM SOLUTIONS, INC. , ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
发明人： ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.
摘要翻译：一种用于对电路进行建模的方法包括：接收网表，其定义多个电路元件之间的多个连接并识别连接的子集。该方法还包括使用具有第一线宽度的第一组线路路由所识别的连接，并且以第二线宽度路由至少一部分剩余的连接。第二线宽小于第一线宽度。该方法还包括用具有第二线宽度的第三组线代替第一组线。

5. 发明申请

WO2009151769A3 SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS 审中-公开
标题翻译：具有改进的互连厚度的连接的系统和方法
公开(公告)号：WO2009151769A3
公开(公告)日：2010-04-22
申请号：PCT/US2009040460
申请日：2009-04-14
申请人： DSM SOLUTIONS INC , ZARKESH-HA PAYMAN , HAMLIN CHRISTOPHER L , KAPOOR ASHOK K , KOFORD JAMES S , VORA MADHUKAR B
发明人： ZARKESH-HA PAYMAN , HAMLIN CHRISTOPHER L , KAPOOR ASHOK K , KOFORD JAMES S , VORA MADHUKAR B
IPC分类号： H01L29/40 , H01L29/80
CPC分类号： H01L23/5283 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.
摘要翻译：一种用于对电路进行建模的方法包括基于限定多个电路元件之间的多个连接的网表生成电路模型。电路模型包括一个或多个电路元件的模型。该方法还包括至少部分地基于与网表相关联的设计规则来确定与至少所选连接相关联的线宽度。另外，该方法包括至少部分地基于与线材厚度相关联的信号延迟来确定与所选择的连接相关联的线材厚度。此外，该方法还包括使用具有基本上等于为连接计算出的线宽度的宽度的线和对于连接计算的线厚度等于电路模型中的所选择的连接来路由选择的连接，并将电路模型存储在电子储存媒介。

6. 发明申请

WO2009151769A2 SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS 审中-公开
标题翻译：具有改进的互连厚度的连接的系统和方法
公开(公告)号：WO2009151769A2
公开(公告)日：2009-12-17
申请号：PCT/US2009/040460
申请日：2009-04-14
申请人： DSM SOLUTIONS, INC. , ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
发明人： ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
CPC分类号： H01L23/5283 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.
摘要翻译：一种用于对电路进行建模的方法包括基于限定多个电路元件之间的多个连接的网表生成电路模型。电路模型包括一个或多个电路元件的模型。该方法还包括至少部分地基于与网表相关联的设计规则来确定与至少所选连接相关联的线宽度。另外，该方法包括至少部分地基于与线材厚度相关联的信号延迟来确定与所选择的连接相关联的线材厚度。此外，该方法还包括使用具有基本上等于为连接计算出的线宽度的宽度的线和对于连接计算的线厚度等于电路模型中的所选择的连接来路由选择的连接，并将电路模型存储在电子储存媒介。

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