专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007098026A3 METHOD AND APPARATUS FOR MONITORING INPUTS TO A COMPUTER 审中-公开
标题翻译：用于监控计算机的方法和装置
公开(公告)号：WO2007098026A3
公开(公告)日：2009-04-09
申请号：PCT/US2007004083
申请日：2007-02-16
申请人： VNS PORTFOLIO LLC , MOORE CHARLES H , FOX JEFFREY ARTHUR , RIBLE JOHN W
发明人： MOORE CHARLES H , FOX JEFFREY ARTHUR , RIBLE JOHN W
IPC分类号： G06F15/00
CPC分类号： G06F15/8007 , G06F1/32 , G06F9/30134 , G06F9/325 , G06F9/3802 , G06F9/3885
摘要： A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise have required an interrupt of an otherwise active computer.
摘要翻译：计算机阵列（10）具有多个计算机（12）。计算机（12）以异步方式彼此通信，并且计算机（12）本身以内部的大致异步方式进行操作。当一台计算机（12）尝试与另一台计算机（12）进行通信时，它将进入休眠状态，直到另一台计算机（12）准备好完成交易，从而节省电力并减少热量产生。休眠计算机（12）可以等待数据或指令（12）。在指令的情况下，睡眠计算机（12）可以等待存储指令或者立即执行指令。在后一种情况下，在首先将指令首先置于存储器中之前，将指令置于指令寄存器（30a）中，当它们被接收和执行时，它们被放置在指令寄存器（30a）中。指令可以包括能够重复执行一系列操作的微循环（100）。在一个应用中，休眠计算机（12）被输入唤醒，使得它开始了否则将需要另外活动的计算机的中断的动作。

2. 发明申请

WO2007117414A2 METHOD AND APPARATUS FOR OPERATING COMPUTER PROCESSOR ARRAY 审中-公开
标题翻译：用于操作计算机处理器阵列的方法和装置
公开(公告)号：WO2007117414A2
公开(公告)日：2007-10-18
申请号：PCT/US2007/008235
申请日：2007-03-30
申请人： TECHNOLOGY PROPERTIES LIMITED , MOORE, Charles, H. , RIBLE, John, W. , FOX, Jeffrey, Arthur
发明人： MOORE, Charles, H. , RIBLE, John, W. , FOX, Jeffrey, Arthur
IPC分类号： G06F9/40
CPC分类号： G06F15/8023 , G06F9/5066 , G06F9/547
摘要： A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 24 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output. Mechanisms are described for communications between computers (12) and the outside environment.
摘要翻译：计算机阵列（10）具有用于完成更大任务的多个计算机（12），其被划分成较小的任务，每个较小的任务分配给一个或多个计算机（12）。每个计算机（12）可以被配置为用于特定功能，并且与外部计算机（12）相关联的各个输入/输出电路（26）特别适用于特定的输入/输出功能。布置在计算机阵列（10）中的24台计算机（12）的示例具有集中式计算核心（34），其中靠近管芯（14）边缘的计算机（12）被配置为用于输入和/或输出。描述了用于计算机（12）和外部环境之间的通信的机制。

3. 发明申请

WO2007098025A2 COMPUTER SYSTEM WITH INCREASED OPERATING EFFICIENCY 审中-公开
标题翻译：具有提高运行效率的计算机系统
公开(公告)号：WO2007098025A2
公开(公告)日：2007-08-30
申请号：PCT/US2007004082
申请日：2007-02-16
申请人： TECHNOLOGY PROPERTIES LTD , MOORE CHARLES H , FOX JEFFREY ARTHUR , RIBLE JOHN W
发明人： MOORE CHARLES H , FOX JEFFREY ARTHUR , RIBLE JOHN W
IPC分类号： G06F15/16
CPC分类号： G06F15/8015
摘要： A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.
摘要翻译：一种微处理器系统，其中处理器阵列通过使用工作模式功能更有效地进行通信。当前不执行代码的处理器保持处于非活动状态，但是在相邻处理器发送任务之前，该状态保持不活动状态。处理器也可以编程为暂时挂起任务以检查传入的任务或消息。

4. 发明申请

WO2007098005A2 MICROLOOP COMPUTER INSTRUCTIONS 审中-公开
标题翻译： MICROLOOP计算机指令
公开(公告)号：WO2007098005A2
公开(公告)日：2007-08-30
申请号：PCT/US2007/004029
申请日：2007-02-16
申请人： TECHNOLOGY PROPERTIES LIMITED , MOORE, Charles, H. , FOX, Jeffrey, Arthur , RIBLE, John, W.
发明人： MOORE, Charles, H. , FOX, Jeffrey, Arthur , RIBLE, John, W.
IPC分类号： G06F15/16
CPC分类号： G06F15/8007 , G06F1/32 , G06F9/30134 , G06F9/325 , G06F9/3802 , G06F9/3885
摘要： A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise have required an interrupt of an otherwise active computer.
摘要翻译：计算机阵列（10）具有多个计算机（12）。计算机（12）以异步方式彼此通信，并且计算机（12）本身以内部的大致异步方式进行操作。当一台计算机（12）尝试与另一台计算机（12）进行通信时，它将进入休眠状态，直到另一台计算机（12）准备好完成交易，从而节省电力并减少热量产生。休眠计算机（12）可以等待数据或指令（12）。在指令的情况下，睡眠计算机（12）可以等待存储指令或者立即执行指令。在后一种情况下，在首先将指令首先置于存储器中之前，将指令置于指令寄存器（30a）中，当它们被接收和执行时，它们被放置在指令寄存器（30a）指令可以包括能够重复执行一系列操作的微循环（100）。在一个应用中，休眠计算机（12）被输入唤醒，使得它开始了否则将需要另外活动的计算机的中断的动作。

5. 发明申请

WO2007098025A3 COMPUTER SYSTEM WITH INCREASED OPERATING EFFICIENCY 审中-公开
公开(公告)号：WO2007098025A3
公开(公告)日：2007-08-30
申请号：PCT/US2007/004082
申请日：2007-02-16
申请人： VNS PORTFOLIO LLC , MOORE, Charles, H. , FOX, Jeffrey, Arthur , RIBLE, John, W.
发明人： MOORE, Charles, H. , FOX, Jeffrey, Arthur , RIBLE, John, W.
IPC分类号： G06F9/46
摘要： A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.

6. 发明申请

WO2008137142A1 METHOD AND APPARATUS FOR LOADING DATA AND INSTRUCTIONS INTO A COMPUTER 审中-公开
标题翻译：用于将数据和指令装入计算机的方法和装置
公开(公告)号：WO2008137142A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/005780
申请日：2008-05-06
申请人： VNS PORTFOLIO LLC , MOORE, Charles, H. , MONTVELISHSKY, Michael, B. , FOX, Jeffrey, Arthur
发明人： MOORE, Charles, H. , MONTVELISHSKY, Michael, B. , FOX, Jeffrey, Arthur
IPC分类号： G06F15/173
CPC分类号： G06F9/4862 , G06F1/3228 , G06F1/3287 , G06F9/3802 , Y02D10/171 , Y02D10/24
摘要： A computer array has a plurality of computers The computers communicate with each other asynchronously, and the computers operate in a generally asynchronous manner internally When one computer attempts to communicate with another it goes to sleep until the other computer is ready to complete the transaction, thereby saving power and reducing heat production The sleeping computer can be awaiting data or instructions in the case of instructions, the sleeping computer can be waiting to store the instructions or to immediately execute the instructions In the later case, the instructions are placed in an instruction register when they are received and executed therefrom, without first placing the instructions first into memory The instructions can include a crawler which is capable of traversing multiple processors along a predefined path and performing a seπes of operations in preselected computers In one application, the crawler performs a stress test into a selected computer
摘要翻译：计算机阵列具有多个计算机计算机彼此异步地通信，并且计算机内部以一般异步的方式操作当一个计算机尝试与另一个计算机进行通信时，它将进入休眠状态，直到另一个计算机准备好完成事务，从而节省电力并减少热量产生睡眠计算机可以在指令的情况下等待数据或指令，睡眠计算机可以等待存储指令或立即执行指令在稍后的情况下，指令被放置在指令寄存器当它们被接收和执行时，而不首先将指令首先放入存储器。指令可以包括爬行器，其能够沿着预定义的路径遍历多个处理器并且在预先选择的计算机中执行操作的分辨率在一个应用中，爬行器执行压力测试进入选定的计算机

7. 发明申请

WO2007098026A2 METHOD AND APPARATUS FOR MONITORING INPUTS TO A COMPUTER 审中-公开
标题翻译：用于监控计算机的方法和装置
公开(公告)号：WO2007098026A2
公开(公告)日：2007-08-30
申请号：PCT/US2007/004083
申请日：2007-02-16
申请人： TECHNOLOGY PROPERTIES LIMITED , MOORE, Charles, H. , FOX, Jeffrey, Arthur , RIBLE, John, W.
发明人： MOORE, Charles, H. , FOX, Jeffrey, Arthur , RIBLE, John, W.
IPC分类号： G06F15/16
CPC分类号： G06F15/8007 , G06F1/32 , G06F9/30134 , G06F9/325 , G06F9/3802 , G06F9/3885
摘要： A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchroπously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise have required an interrupt of an otherwise active computer.
摘要翻译：计算机阵列（10）具有多个计算机（12）。计算机（12）彼此非常通信，并且计算机（12）本身以内部的大致异步方式工作。当一台计算机（12）尝试与另一台计算机（12）进行通信时，它将进入休眠状态，直到另一台计算机（12）准备好完成交易，从而节省电力并减少热量产生。休眠计算机（12）可以等待数据或指令（12）。在指令的情况下，睡眠计算机（12）可以等待存储指令或者立即执行指令。在后一种情况下，在首先将指令首先置于存储器中之前，将指令置于指令寄存器（30a）中，当它们被接收和执行时，它们被放置在指令寄存器（30a）指令可以包括能够重复执行一系列操作的微循环（100）。在一个应用中，休眠计算机（12）被输入唤醒，使得它开始了否则将需要另外活动的计算机的中断的动作。

8. 发明申请

WO2009128937A3 METHOD AND APPARATUS FOR ARRANGING MULTIPLE PROCESSORS ON A SEMICONDUCTOR CHIP 审中-公开
标题翻译：用于在半导体芯片上安装多个处理器的方法和装置
公开(公告)号：WO2009128937A3
公开(公告)日：2010-01-14
申请号：PCT/US2009002395
申请日：2009-04-17
申请人： VNS PORTFOLIO LLC , MOORE CHARLES H , FOX JEFFREY ARTHUR , RIBLE JOHN W
发明人： MOORE CHARLES H , FOX JEFFREY ARTHUR , RIBLE JOHN W
IPC分类号： G06F9/46
CPC分类号： G06F15/8023
摘要： A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses.
摘要翻译：一种用于连接多个核以形成多核处理器的方法和装置。每个处理器连接到至少两个其他处理器，每个处理器是第一处理器的镜像。处理器被连接以形成由一个总线连接的二维矩阵。

9. 发明申请

WO2007117414A3 METHOD AND APPARATUS FOR OPERATING COMPUTER PROCESSOR ARRAY 审中-公开
标题翻译：用于操作计算机处理器阵列的方法和装置
公开(公告)号：WO2007117414A3
公开(公告)日：2008-11-20
申请号：PCT/US2007008235
申请日：2007-03-30
申请人： VNS PORTFOLIO LLC , MOORE CHARLES H , RIBLE JOHN W , FOX JEFFREY ARTHUR
发明人： MOORE CHARLES H , RIBLE JOHN W , FOX JEFFREY ARTHUR
IPC分类号： G06F3/00 , G06F15/00 , G06F15/76
CPC分类号： G06F15/8023 , G06F9/5066 , G06F9/547
摘要： A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 24 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output. Mechanisms are described for communications between computers (12) and the outside environment.
摘要翻译：计算机阵列（10）具有多个计算机（12），用于完成更大的任务，其被分成较小的任务，每个较小的任务分配给一个或多个计算机（12）。每个计算机（12）可以被配置为用于特定功能，并且与外部计算机（12）相关联的各个输入/输出电路（26）特别适用于特定的输入/输出功能。布置在计算机阵列（10）中的24台计算机（12）的示例具有集中计算核心（34），其中计算机（12）更靠近管芯（14）的边缘被配置为用于输入和/或输出。描述了用于计算机（12）和外部环境之间的通信的机制。

10. 发明申请

WO2009145821A1 MICROPROCESSOR COMMUNICATIONS SYSTEM 审中-公开
标题翻译：微处理器通信系统
公开(公告)号：WO2009145821A1
公开(公告)日：2009-12-03
申请号：PCT/US2009/001975
申请日：2009-03-31
申请人： VNS PORTFOLIO LLC , MOORE, Charles, H. , FOX, Jeffrey, Arthur , RIBLE, John, W.
发明人： MOORE, Charles, H. , FOX, Jeffrey, Arthur , RIBLE, John, W.
IPC分类号： G06F9/46
CPC分类号： G06F15/17
摘要： A microprocessor communications system utilizes a combination of an activity status monitor register and one or more address select registers to read from a communications port of one processor and write to a communications port of an adjacent processor in a single instruction word loop. This circumvents the requirement to save and retrieve data and/or instructions from memory. A stack register selector contains a plurality of stack registers and a plurality of shift registers, which are interconnected. The stack registers are selected by the shift registers in such a way that the stack registers operate in a circular repeating pattern, which prevents overflow and underflow of stacks.
摘要翻译：微处理器通信系统利用活动状态监视寄存器和一个或多个地址选择寄存器的组合来从一个处理器的通信端口读取并且在单个指令字循环中写入相邻处理器的通信端口。这避免了从内存中保存和检索数据和/或指令的要求。堆栈寄存器选择器包含互连的多个堆栈寄存器和多个移位寄存器。堆栈寄存器由移位寄存器选择，使得堆栈寄存器以圆形重复模式操作，这防止堆栈的上溢和下溢。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式