专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2005024556A3 SYSTEM AND METHOD FOR DIRECT MEMORY ACCESS FROM HOST WITHOUT PROCESSOR INTERVENTION WHEREI AUTOMATIC ACCESS TO MEMORY DURING HOST START UP DOES NOT OCCUR 审中-公开
标题翻译：用于直接存储器访问主机的系统和方法，无需处理器干预，在主机启动期间自动访问存储器不会发生
公开(公告)号：WO2005024556A3
公开(公告)日：2009-04-16
申请号：PCT/US2004025252
申请日：2004-08-04
申请人： EMULEX DESIGN & MFG CORP , MILLER EDDIE , DUCKMAN DAVID JAMES , BUTLER JIM DONALD , JIN DAMING , TANG JOHN SUI-KEI
发明人： MILLER EDDIE , DUCKMAN DAVID JAMES , BUTLER JIM DONALD , JIN DAMING , TANG JOHN SUI-KEI
IPC分类号： G06F13/28 , G06F20060101 , G06F12/00 , G06F13/38
CPC分类号： G06F13/385 , G06F13/28
摘要： A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash, Fig. 4) located on a peripheral device (e.g., HBA, Fig. 4), without the assistance of a microprocessor (52) located on the peripheral device (80). In a preferred embodiment, new host registers (82) are implemented within controller circuitry of the peripheral device, the host registers being configured to be recognized by host software executed by host. The host device reads and writes to the host registers, which causes appropriate controller hardware to acces the peripheral nonvolatile memory accordingly. By creating and implementing the new host registers, an enhanced controller is created that allows a host device to directly access peripheral memory, without peripheral processor assistance.
摘要翻译：一种用于允许主机设备（例如，服务器）对位于外围设备（例如，HBA，图4）上的外围存储器（例如，闪存，图4）进行编程的直接访问的方法和系统，位于外围设备（80）上的微处理器（52）。在优选实施例中，新的主机寄存器（82）被实现在外围设备的控制器电路内，主机寄存器被配置为由主机执行的主机软件识别。主机设备读取和写入主机寄存器，从而使适当的控制器硬件相应地访问外设非易失性存储器。通过创建和实现新的主机寄存器，创建一个增强的控制器，允许主机设备直接访问外围存储器，而无需外设处理器的帮助。

2. 发明申请

WO2005024555A3 MULTI-CHANNEL MEMORY ACCESS ARBITRATION METHOD AND SYSTEM 审中-公开
标题翻译：多通道存储器访问仲裁方法和系统
公开(公告)号：WO2005024555A3
公开(公告)日：2006-02-02
申请号：PCT/US2004025251
申请日：2004-08-04
申请人： EMULEX DESIGN & MFG CORP , MILLER EDDIE , DUCKMAN DAVID JAMES , BUTLER JIM DONALD , HUYNH KHANH HUE
发明人： MILLER EDDIE , DUCKMAN DAVID JAMES , BUTLER JIM DONALD , HUYNH KHANH HUE
IPC分类号： G06F20060101 , G06F12/00 , G06F13/00
CPC分类号： G06F9/526
摘要： A method and system for allowing flexible control of access to a shared memory by multiple requesters. In a preferred embodiment, the invention arbitrates access to flash memory on a HBA between multiple host channels and HBA microprocessors, and eliminates contention possibilities for the flash during write cycles by the allowing a grant to be locked for a period defined by the flash write protocol and timing.
摘要翻译：一种用于允许灵活控制多个请求者对共享存储器的访问的方法和系统。在优选实施例中，本发明仲裁在多个主机信道和HBA微处理器之间的HBA上对闪存的访问，并且通过允许将许可锁定在由闪存写协议定义的时间段内，在写周期期间消除闪存的争用可能性和时机。

3. 发明申请

WO2004072799A3 ZERO CONFIGURATION AUTO-DISCOVERY FOR NETWORK STORAGE 审中-公开
标题翻译：零配置自动发现网络存储
公开(公告)号：WO2004072799A3
公开(公告)日：2005-12-22
申请号：PCT/US2004003672
申请日：2004-02-06
申请人： EMULEX DESIGN & MFG CORP
发明人： JONES MARC TIMOTHY
IPC分类号： H04L29/06 , G06F15/177
CPC分类号： H04L69/16 , H04L69/161 , H04L69/165
摘要： An adapter for a client (125) of a storage network (120) may perform a port scan on the network to identify storage targets (110), e.g., (Internet SCSI (Small Computer System Interface)) targets. The adapter may then send a resource discovery command to the identified storage targets to identify available storage resource(s) at the storage targets.
摘要翻译：用于存储网络（120）的客户端（125）的适配器可以在网络上执行端口扫描以识别例如（因特网SCSI（小型计算机系统接口））目标的存储目标（110）。适配器然后可以向所识别的存储目标发送资源发现命令，以识别存储目标处的可用存储资源。

4. 发明申请

WO2004104730A3 DYNAMICALLY SELF-ADJUSTING POLLING MECHANISM 审中-公开
标题翻译：动态自调节机构
公开(公告)号：WO2004104730A3
公开(公告)日：2005-04-28
申请号：PCT/US2004014217
申请日：2004-05-07
申请人： EMULEX DESIGN & MFG CORP , BARRETT DAVID MICHAEL
发明人： BARRETT DAVID MICHAEL
IPC分类号： G06F20060101 , G06F3/00 , G06F3/06 , G06F13/14
CPC分类号： G06F11/0787 , G06F11/0745
摘要： A system and method is disclosed for preventing the loss of event messages due to message buffer overruns. A fixed vendor-specific buffer pool is loaded with log messages by firmware in an adapter. A service application periodically polls a device driver for messages in the buffer pool. The device driver responds with the number of messages stored in the buffer pool and the total number of buffers in the buffer pool. The service application then issues "get next message" requests to receive the stored messages. Once the buffer pool has been emptied, the service application writes the messages to a disk file. The service application then computes a percent utilization of the buffer pool, and if the percent utilization exceeds a predetermined threshold, an algorithm is employed for increasing the polling frequency. If the percent utilization is below the threshold, an algorithm is employed for decreasing the polling frequency.
摘要翻译：公开了一种用于防止由于消息缓存超限而导致的事件消息丢失的系统和方法。固定的供应商特定的缓冲池通过固件在适配器中加载日志消息。服务应用程序定期轮询设备驱动程序以获取缓冲池中的消息。设备驱动程序使用缓冲池中存储的消息数量和缓冲池中的缓冲区总数进行响应。服务应用程序然后发出“获取下一个消息”请求以接收存储的消息。一旦缓冲池已经清空，服务应用程序将消息写入磁盘文件。然后，服务应用程序计算缓冲池的百分比利用率，如果百分比利用率超过预定阈值，则采用一种算法来增加轮询频率。如果百分比利用率低于阈值，则采用一种算法来减少轮询频率。

5. 发明申请

WO2004088462A3 HARDWARE ASSISTED FIRMWARE TASK SCHEDULING AND MANAGEMENT 审中-公开
标题翻译：硬件协助固件任务调度和管理
公开(公告)号：WO2004088462A3
公开(公告)日：2005-02-03
申请号：PCT/US2004009197
申请日：2004-03-26
申请人： EMULEX DESIGN & MFG CORP
发明人： SPENCER THOMAS VINCENT
IPC分类号： G06F20060101 , G06F9/00 , G06F9/46 , G06F9/50 , G06F13/38
CPC分类号： G06F9/546 , G06F2209/548
摘要： A data processing module (10) having a central processing unit (100) and a task management control method and apparatus is disclosed which may comprise: a plurality of task identifiers adapted to identify a task requesting service by the central processing unit (100), an arbitration system (210) external to the central processing unit (100) adapted to select a task identifier from one of the plurality of task identifiers and to provide to the central processing unit (100) the location of data or at least one instruction, which location is determined by the identity of the task identifier and to provide to the central processing unit (100) the location of at least one instruction to initiate processing of the task, comprising: arbitration value determination logic (210) adapted to determine at least one arbitration value of each task identifier requesting service; arbitration logic (210) adapted to select a task identifier requesting service.
摘要翻译：公开了一种具有中央处理单元（100）和任务管理控制方法和装置的数据处理模块（10），其可包括：多个任务标识符，用于识别中央处理单元（100）的任务请求服务，中央处理单元（100）外部的仲裁系统（210），适于从所述多个任务标识符之一中选择任务标识符，并向中央处理单元（100）提供数据或至少一个指令的位置，所述位置由所述任务标识符的身份确定，并且向所述中央处理单元（100）提供至少一个指令以启动所述任务的处理的位置，包括：仲裁值确定逻辑（210），适于至少确定每个任务标识符请求服务的一个仲裁值; 适于选择任务标识符请求服务的仲裁逻辑（210）。

6. 发明申请

WO2004063850A3 MANAGING MEMORY BY USING A FREE BUFFER POOL 审中-公开
标题翻译：使用免费缓冲池管理内存
公开(公告)号：WO2004063850A3
公开(公告)日：2004-12-23
申请号：PCT/US0340967
申请日：2003-12-19
申请人： EMULEX DESIGN & MFG CORP
发明人： CLAYTON SHAWN ADAM , MCMASTER SHAUN , SPENCER THOMAS V
IPC分类号： G06F20060101 , G06F9/50 , G06F12/00
CPC分类号： G06F9/5016
摘要： A method includes receiving a first buffer allocation command from a first processor, the allocation command including a register address associated with a pool of buffers in a shared memory, determining whether a buffer is available in the buffer pool based upon a buffer index corresponding to a free buffer, and if a buffer is determined available allocating the buffer to the first processor.
摘要翻译：一种方法包括从第一处理器接收第一缓冲器分配命令，所述分配命令包括与共享存储器中的缓冲器池相关联的寄存器地址，基于与缓冲器索引对应的缓冲器索引来确定缓冲器池中是否可用缓冲器并且如果缓冲器被确定可用，则将缓冲器分配给第一处理器。

7. 发明申请

WO2004091053A2 VIRTUAL PERIPHERAL COMPONENT INTERCONNECT MULTIPLE-FUNCTION DEVICE 审中-公开
标题翻译：虚拟外设组件互连多功能设备
公开(公告)号：WO2004091053A2
公开(公告)日：2004-10-21
申请号：PCT/US2004009802
申请日：2004-03-31
申请人： EMULEX DESIGN & MFG CORP
发明人： CLAYTON SHAWN ADAM
IPC分类号： G06F3/00 , G06F9/00 , G06F13/00 , G06F13/10 , G06F13/14 , G06F13/38 , H01R20060101 , H01R
CPC分类号： G06F13/385
摘要： A peripheral component interconnect (PCI) device comprising a bus interface coupled to a component interconnect bus, a plurality of configuration space register sets, and virtual multiple-function logic. Each set of configuration space registers is associated with a function. The virtual multiple-function logic is coupled to the bus interface and the configuration space register sets. The virtual multiple-function logic provides access to a plurality of configuration space registers for a plurality of functions. The virtual multiple-function logic also enables a plurality of functions to share the bus interface and other internal logic.
摘要翻译：包括耦合到组件互连总线，多个配置空间寄存器组和虚拟多功能逻辑的总线接口的外围组件互连（PCI）设备。每组配置空间寄存器与一个功能相关联。虚拟多功能逻辑耦合到总线接口和配置空间寄存器集合。虚拟多功能逻辑提供对多个功能的多个配置空间寄存器的访问。虚拟多功能逻辑还使多个功能能够共享总线接口和其他内部逻辑。

8. 发明申请

WO2005036313A3 QUEUE REGISTER CONFIGURATION STRUCTURE 审中-公开
标题翻译：队列寄存器配置结构
公开(公告)号：WO2005036313A3
公开(公告)日：2005-12-22
申请号：PCT/US2004025387
申请日：2004-08-26
申请人： EMULEX DESIGN & MFG CORP , DUCKMAN DAVID JAMES
发明人： DUCKMAN DAVID JAMES
IPC分类号： G06F9/46 , H04L29/08 , G06F13/00
CPC分类号： G06F9/546 , H04L67/1097 , H04L69/329
摘要： Generalized queues (404) and specialized registers (420) associated with the generalized queues are disclosed for coordinating the passing of information between two tightly coupled processors (408 and (410). The capacity of the queues can be adjusted to match the current environment, with no limit on the size of the entry as agreed upon between the sending and receiving processors, and with no practical limit on the number of the entries or restrictions on where the entries appear. In addition, the specialized registers allow for immediate notifications of queue and other conditions, selectively in receiving and generating conditions, and the ability to combine data transfer and particular condition notifications in the same attention register.
摘要翻译：公开了与广义队列相关联的广义队列（404）和专用寄存器（420），用于协调两个紧密耦合的处理器之间的信息传递（408和（410）），可调整队列的容量以匹配当前环境，对发送和接收处理器之间商定的条目的大小没有限制，对于条目出现的条目数量或限制没有实际限制。此外，专用寄存器允许立即通知队列和其他条件，选择性地接收和产生条件，以及将数据传输和特定条件通知组合在同一关注寄存器中的能力。

9. 发明申请

WO2004064286A3 FLOW-THROUGH REGISTER 审中-公开
标题翻译：流通注册
公开(公告)号：WO2004064286A3
公开(公告)日：2005-12-15
申请号：PCT/US0338841
申请日：2003-12-05
申请人： EMULEX DESIGN & MFG CORP
发明人： SCORDALAKES NICHOLAS EMMANUEL
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4081 , G06F13/405
摘要： A selectively transparent interface circuit identified herein as a flow-through register (FTR) is disclosed. The FTR enables one or more devices on a primary bus to communicate with a device on a secondary bus without incurring the latency and performance degradation of conventional bridges. The FTR can also provide Hot Swap capability which allows, for example, a device designed for a regular PCI bus to be plugged into a CompactPCl bus while system power remains on. The synchronous flow-through nature of the FTR eliminates the need for large data buffers that would otherwise result in transaction delays and performance degradation. Unlike other types of non-transparent devices such as PCI-to-PCI bridges, the FTR does not occupy any configuration space and is fully transparent to the host and HBA device driver software during flow-through operation, eliminating the need for costly changes to host and device driver firmware/software.
摘要翻译：本文中公开了一种选择性透明的接口电路作为流通寄存器（FTR）。 FTR使主总线上的一个或多个设备能够与辅助总线上的设备通信，而不会导致传统桥接器的延迟和性能下降。 FTR还可以提供热插拔功能，例如，允许将常规PCI总线设计的设备插入CompactPCl总线，同时系统电源保持开启状态。 FTR的同步流通性消除了对大数据缓冲区的需求，否则会导致事务延迟和性能下降。与其他类型的非透明设备（如PCI到PCI桥接器）不同，FTR不会占用任何配置空间，并且在流通操作期间对主机和HBA设备驱动程序软件完全透明，从而无需花费昂贵的更改主机和设备驱动程序固件/软件。

10. 发明申请

WO2005006124A3 READ/WRITE COMMAND BUFFER POOL RESOURCE MANAGEMENT USING READ-PATH PREDICTION OF FUTURE RESOURCES 审中-公开
标题翻译：使用读取路径预测未来资源的读/写命令缓冲池资源管理
公开(公告)号：WO2005006124A3
公开(公告)日：2005-08-04
申请号：PCT/US2004017759
申请日：2004-06-04
申请人： EMULEX DESIGN & MFG CORP , JACKSON THOMAS PATRICK , NOTTBERG CURTIS EDWARD , WILEY DAVID ROBERT , JONES MARK TIMOTHY
发明人： JACKSON THOMAS PATRICK , NOTTBERG CURTIS EDWARD , WILEY DAVID ROBERT , JONES MARK TIMOTHY
IPC分类号： G06F20060101 , G06F13/14 , G06F13/38
CPC分类号： G06F13/385
摘要： A method for managing read and write data congestion in a system for executing write and read data commands and having a buffer pool of blocks for temporarily storing read and write data is disclosed. Management of the buffer pool and the initiation of read and write commands ensures that free blocks are available to temporarily store read data arriving at a host bus adapter (HBA). If the currently available blocks would be substantially consumed by the total outstanding inbound read data requested, no more write data commands will be initiated. As inbound read data is received into the buffer pool and subsequently transferred out of the buffer pool to the initiator device, the blocks in the buffer pool are freed up. When the read data transfer is completed and sufficient buffer resources have been freed up, read and write data commands may resume.
摘要翻译：公开了一种用于管理用于执行写入和读取数据命令的系统中的读取和写入数据拥塞并且具有用于临时存储读取和写入数据的块的缓冲池的方法。管理缓冲池并启动读取和写入命令可确保空闲块可用于临时存储到达主机总线适配器（HBA）的读取数据。如果当前可用块将基本上被请求的未完成入站读取数据消耗，则不会再发起写入数据命令。随着入站读取数据被接收到缓冲池中并随后从缓冲池传送到启动设备，缓冲池中的块被释放。当读数据传输完成并且有足够的缓冲资源被释放时，可以恢复读和写数据命令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式