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1. 发明申请

WO2007117618A3 SYSTEM AND METHOD FOR VOLTAGE NOISE AND JITTER MEASUREMENT USING TIME-RESOLVED EMISSION 审中-公开
公开(公告)号：WO2007117618A3
公开(公告)日：2007-10-18
申请号：PCT/US2007/008607
申请日：2007-04-05
申请人： CREDENCE SYSTEMS CORPORATION , KASAPI, Steven , WOODS, Gary Leonard
发明人： KASAPI, Steven , WOODS, Gary Leonard
IPC分类号： G01R23/16
摘要： Time-resolved emission can be used to measure loop-synchronous, small-signal voltage perturbation in integrated circuits. In this technique the measurements are completely non-invasive and so reflect the true device behavior. The time-dependant propagation delay caused by Vdd modulation also shows the expected qualitative signature. This technique should find applications in circuits with relatively fast clock-like circuits where loop-synchronous voltage pickup is limiting circuit behavior.

2. 发明申请

WO1998031099A1 TIMING SIGNAL GENERATOR 审中-公开
标题翻译：定时信号发生器
公开(公告)号：WO1998031099A1
公开(公告)日：1998-07-16
申请号：PCT/US1997020336
申请日：1997-11-04
申请人： CREDENCE SYSTEMS CORPORATION
发明人： CREDENCE SYSTEMS CORPORATION , CHAPMAN, Douglas, J. , CURRIN, Jeffrey, D. , KUGLIN, Philip, Theodore
IPC分类号： H03K05/26
CPC分类号： H03K5/131 , G01R31/31922 , G06F1/04
摘要： A timing signal generator (10) adjustably times successive pulses of an output timing signal (TIMING-). Generator (10) includes a circuit (24) for providing a set of 2N phase signals (PH0-PH16) having frequency locked to a clock signal (CLOCK). First and second selectors (25, 27) sample the data once per cycle of the clock signal (CLOCK). First selector (25) determines whether a first output signal (OUTA) is produced and which of the first N phase signals is selected for controlling timing of the first output signal (OUTA). Second selector (27) determines whether a second output signal (OUTB) is produced and which of the second N phase signals is selected for controlling the second output signal (OUTB). First and second output signals (OUTA, OUTB) are logically ORed to produce the timing signal (TIMING-). Timing of data sampling by each selector (25, 27) is separately adjusted so that the output signals (OUTA, OUTB) change state only when the selected phase signal changes state, not when the selector (25, 27) changes its selection in response to new input data.
摘要翻译：定时信号发生器（10）可调节地输出定时信号（TIMING-）的连续脉冲。发电机（10）包括用于提供具有频率锁定到时钟信号（CLOCK）的一组2N相位信号（PH0-PH16）的电路（24）。第一和第二选择器（25,27）每个周期的时钟信号（CLOCK）对数据进行一次采样。第一选择器（25）确定是否产生第一输出信号（OUTA）和选择第一N相信号中的哪一个来控制第一输出信号（OUTA）的定时。第二选择器（27）确定是否产生第二输出信号（OUTB），并且选择第二N相信号中的哪一个来控制第二输出信号（OUTB）。第一和第二输出信号（OUTA，OUTB）进行逻辑或运算以产生定时信号（TIMING-）。分别调整每个选择器（25,27）进行数据采样的定时，使得只有当选择的相位信号改变状态时，输出信号（OUTA，OUTB）才改变状态，而不是当选择器（25,27）响应时改变其选择到新的输入数据。

3. 发明申请

WO1997022916A1 TIMING SIGNAL GENERATOR 审中-公开
标题翻译：定时信号发生器
公开(公告)号：WO1997022916A1
公开(公告)日：1997-06-26
申请号：PCT/US1996018849
申请日：1996-11-21
申请人： CREDENCE SYSTEMS CORPORATION
发明人： CREDENCE SYSTEMS CORPORATION , LESMEISTER, Gary, J. , BEDELL, Daniel, J.
IPC分类号： G06F01/04
CPC分类号： G01R31/2851 , G01R31/31813 , G01R31/31907 , G01R31/3191 , G01R31/31921 , G01R31/31922 , G06F1/025 , G06F1/04
摘要： A timing signal generator (10) includes a voltage controlled oscillator (VCO) (14), a logic circuit (21), N set circuits (19), N reset circuits (20) and a bistable latch circuit (23). The VCO produces a set of N reference signals (T1-TN) frequency locked to a reference clock signal (T1) and distributed in phase so as to evenly resolve the reference clock period into N intervals. The logic circuit (21) asserts ones of N set signals (SE1-SEN) and N reset signals (RE1-REN) selected by input control words. The timing of leading and trailing edges of pulses of the output timing signal (26) may be controlled with a resolution that is 1/Nth of the period of the reference clock by supplying an appropriate control word sequence to the logic circuit.
摘要翻译：定时信号发生器（10）包括压控振荡器（VCO）（14），逻辑电路（21），N组电路（19），N个复位电路（20）和双稳态锁存电路（23）。 VCO产生频率锁定到参考时钟信号（T1）的N个参考信号（T1-TN）的集合并且相位分布，以将参考时钟周期均匀地分解为N个间隔。逻辑电路（21）断言由输入控制字选择的N个置位信号（SE1-SEN）和N个复位信号（RE1-REN）中的一个。输出定时信号（26）的脉冲的前沿和后沿的定时可以通过向逻辑电路提供适当的控制字序列，以基准时钟周期的1 / N的分辨率来控制。

4. 发明申请

WO2008122016A1 A MULTI-TYPE TEST INTERFACE SYSTEM AND METHOD 审中-公开
标题翻译：多类型测试接口系统和方法
公开(公告)号：WO2008122016A1
公开(公告)日：2008-10-09
申请号：PCT/US2008/059052
申请日：2008-04-01
申请人： CREDENCE SYSTEMS CORPORATION , SKALA, Ken , CURRIN, Jeff , HAINDS, Curtis , RAMOS, Carlos
发明人： SKALA, Ken , CURRIN, Jeff , HAINDS, Curtis , RAMOS, Carlos
IPC分类号： H01L21/66 , G01R31/28
CPC分类号： G01R31/2808 , G06F11/2733
摘要： Efficient automated testing systems and methods are presented. In one embodiment, an automated testing system includes a plurality of bucket modules, and a device under test transition interface. The plurality of bucket modules have similar external connection form factors for a variety of instruments. The interface is for transitioning connections from the plurality of bucket modules to a device under test.
摘要翻译：提出了高效的自动化测试系统和方法。在一个实施例中，自动测试系统包括多个桶模块和被测设备转换接口。多个桶模块具有用于各种仪器的类似的外部连接形状因子。该接口用于将连接从多个桶模块转换到被测设备。

5. 发明申请

WO1997040576A1 FREQUENCY MULTIPLIER 审中-公开
标题翻译：频率乘法器
公开(公告)号：WO1997040576A1
公开(公告)日：1997-10-30
申请号：PCT/US1997006367
申请日：1997-04-16
申请人： CREDENCE SYSTEMS CORPORATION
发明人： CREDENCE SYSTEMS CORPORATION , MILLER, Charles, A.
IPC分类号： H03B19/00
CPC分类号： H03L7/0812 , H03B19/00 , H03B2200/009 , H03K5/00006 , H03L7/16
摘要： A frequency multiplier includes a set of substantially identical inverters (G1-G8) connected in series for successively delaying an input periodic reference signal (T0) to produce a set of inverter output signals. A phase controller (14, 18) adjusts the delay provided by each inverter so that the output signal of a last inverter (T8) of the series is phase-locked to a reference signal supplied as input to the first inverter of the series. Thus, the inverter outputs are evenly distributed in phase with pulse edges evenly dividing the period of the reference signal. A set of XOR gates (X1-X3) logically combine selected inverter output signals to produce periodic output signals of frequencies which are even multiples of the reference signal.
摘要翻译：倍频器包括一组基本相同的反相器（G1-G8），其串联连接以连续延迟输入周期性参考信号（T0）以产生一组反相器输出信号。相位控制器（14,18）调整每个逆变器提供的延迟，使得串联的最后一个反相器（T8）的输出信号被锁相到作为串联的第一反相器的输入提供的参考信号。因此，逆变器输出均匀分布在均匀分布参考信号周期的脉冲边沿。一组XOR门（X1-X3）逻辑组合所选的反相器输出信号，以产生频率的周期性输出信号，其频率是参考信号的偶数倍。

6. 发明申请

WO1997012254A1 PARALLEL PROCESSING INTEGRATED CIRCUIT TESTER 审中-公开
标题翻译：并行处理集成电路测试仪
公开(公告)号：WO1997012254A1
公开(公告)日：1997-04-03
申请号：PCT/US1996014728
申请日：1996-09-10
申请人： CREDENCE SYSTEMS CORPORATION
发明人： CREDENCE SYSTEMS CORPORATION , LESMEISTER, Gary, J.
IPC分类号： G01R31/28
CPC分类号： G01R31/31813 , G01R31/2851 , G01R31/31907 , G01R31/3191 , G01R31/31921 , G01R31/31922 , G06F1/025 , G06F1/04
摘要： An integrated circuit tester (10) includes several processing nodes (14), one node associated with each terminal of an integrated circuit device under test (DUT) (12). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output signal produced at the DUT terminal. Each node (14) includes a memory (34) for storing algorithmic instructions for generating a set of commands indicating when a test signal is to be transmitted to the associated terminal and indicating when a DUT output at the associated node is to be sampled. Each node also includes a processor (36) for processing the algorithmic instructions to produce the commands. Each node further includes circuits (40) responsive to the commands for transmitting the test signals to the associated DUT terminal and for sampling the DUT output produced at the associated DUT terminal at times indicated by the commands.
摘要翻译：集成电路测试器（10）包括若干处理节点（14），与被测集成电路设备（DUT）（12）的每个终端相关联的一个节点。在精确确定的时间，每个节点产生一个测试信号并发送给相关联的DUT终端，或采样在DUT终端产生的DUT输出信号。每个节点（14）包括存储器（34），用于存储算法指令，用于产生一组命令，该命令指示何时将测试信号发送到相关联的终端，并且指示何时将对相关节点的DUT输出进行采样。每个节点还包括用于处理算法指令以产生命令的处理器（36）。每个节点还包括响应于用于将测试信号发送到相关联的DUT终端的命令的电路（40），并且用于在由命令指示的时间对在相关联的DUT终端产生的DUT输出进行采样。

7. 发明申请

WO1994017592A1 RETRIGGERED OSCILLATOR FOR JITTER-FREE PHASE LOCKED LOOP FREQUENCY SYNTHESIS 审中-公开
标题翻译：无抖动振荡器，无锁相环锁频合成
公开(公告)号：WO1994017592A1
公开(公告)日：1994-08-04
申请号：PCT/US1994000696
申请日：1994-01-18
申请人： CREDENCE SYSTEMS CORPORATION
发明人： CREDENCE SYSTEMS CORPORATION , LESMEISTER, Gary, J.
IPC分类号： H03K05/26
CPC分类号： G01R31/31709 , G01R31/3191 , H03K5/135 , H03K5/15 , H03L7/081 , H03L7/087
摘要： A retriggered oscillator time base including a phase lock loop controlled ring (54) for direct retriggering by a reference oscillator (52). The ring (54) has taps (55) at various successive stages that are outputs to an on-the-fly selector (58) that can add any ten-bit value to a current-tap selection to enable a next-tap selection. Such on-the-fly addition can increase the period of a signal each cycle and thereby divide the reference frequency. Ring's outputs (55) are also used to drive two other retriggered rings (72, 74) for a plurality of NANO timing generators. The use of two rings allows retriggering of one of the rings before the other has completed a whole one-shot cycle. An on-the-fly selector (76) subtracts a value from a present NANO select to a next NANO select to convert back the timebase to the fixed reference frequency for phase and frequency comparison. The subtraction acts as a frequency multiplication whose output Tofx is equal to the reference frequency.
摘要翻译：一种重新触发的振荡器时基，包括用于由参考振荡器（52）直接重新触发的锁相环控制环（54）。环（54）具有在各种连续阶段的抽头（55），其是输出到动态选择器（58），其可以将任何十位值添加到当前抽头选择以启用下一抽头选择。这种即时添加可以增加每个周期的信号的周期，从而划分参考频率。环的输出（55）也用于驱动多个NANO定时发生器的另外两个重新触发的环（72,74）。使用两个环可以使其中一个环重新触发，而另一个环已经完成了整个单次循环。动态选择器（76）从当前NANO选择中减去值到下一个NANO选择，以将时基转换为用于相位和频率比较的固定参考频率。减法作为输出Tofx等于参考频率的倍频。

8. 发明申请

WO2006086637A1 APPARATUS AND METHOD FOR HARD-DOCK A TESTER TO A TILTABLE IMAGER 审中-公开
标题翻译：用于将测试仪硬化到可倾斜成像仪的装置和方法
公开(公告)号：WO2006086637A1
公开(公告)日：2006-08-17
申请号：PCT/US2006/004743
申请日：2006-02-10
申请人： CREDENCE SYSTEMS CORPORATION , FRANK, Jonathan , PORTUNE, Rick
发明人： FRANK, Jonathan , PORTUNE, Rick
IPC分类号： G01R31/311 , G01R31/28
CPC分类号： G01R31/311 , G01N21/9501 , G01R31/2887
摘要： An apparatus and method are disclosed for hard-docking of a tester head to a DUT, while permitting the angular alignment of a specimen to be inspected to the optical axis of an optical testing tool. In one example, a system for orthogonal alignment of a specimen to an optical axis of a collection optics is provided. The system comprises a self-leveling tabletop; a specimen holder coupled to the tabletop and held at a fix orientation; collection optics coupled to the tabletop; a plunger coupled to the tabletop and operable to maintain the leveling orientation of the tabletop; a control valve sensing the leveling orientation of the tabletop and coupled to the plunger to control the operation of the plunger; and an aligner coupled to the tabletop and operable to change the alignment of the optical axis of the collection optics with respect to the specimen without changing the fixed orientation of the specimen holder.
摘要翻译：公开了一种用于将测试器头硬接合到DUT的装置和方法，同时允许检查样本的角度对准到光学测试工具的光轴。在一个示例中，提供了用于样本与收集光学器件的光轴正交对准的系统。该系统包括自流平台式; 联接到桌面并保持在固定方向的样本保持器; 收集光学耦合到桌面; 联接到桌面并可操作以保持桌面的调平方向的柱塞; 感测台面的调平方向并联接到柱塞以控制柱塞的操作的控制阀; 以及对准器，其联接到桌面并且可操作以相对于样本改变收集光学器件的光轴的对准，而不改变样本保持器的固定取向。

9. 发明申请

WO2004113942A1 METHOD FOR FAULT LOCALIZATION IN CIRCUITS 审中-公开
标题翻译：电路故障定位方法
公开(公告)号：WO2004113942A1
公开(公告)日：2004-12-29
申请号：PCT/US2004/019975
申请日：2004-06-21
申请人： CREDENCE SYSTEMS CORPORATION , LEIBOWITZ, Martin , LUNDQUIST, Theodore, R. , SHAH, Ketan , DESPLATS, Romain , PERDU, Philippe
发明人： LEIBOWITZ, Martin , LUNDQUIST, Theodore, R. , SHAH, Ketan , DESPLATS, Romain , PERDU, Philippe
IPC分类号： G01R31/3183
CPC分类号： G01R31/31728 , G01R31/311
摘要： Methods for using measured time resolved photon emission data and simulated time resolved photon emission data for fault localization are provided and described. In one embodiment, a method of localizing a fault in a circuit includes generating simulation photon emission data for the circuit. Moreover, measured photon emission data for the circuit is generated. The simulation photon emission data is compared with the measured photon emission data to generate a comparison result. Further, the comparison result is classified according to predetermined criteria. The classified comparison result is used in a fault localization technique to determine next action in localizing the fault.
摘要翻译：提供并描述了使用测量的时间分辨光子发射数据和用于故障定位的模拟时间分辨光子发射数据的方法。在一个实施例中，定位电路中的故障的方法包括产生电路的模拟光子发射数据。此外，产生用于电路的测量的光子发射数据。将模拟光子发射数据与测量的光子发射数据进行比较以产生比较结果。此外，根据预定标准对比较结果进行分类。分类比较结果用于故障定位技术，以确定定位故障的下一步动作。

10. 发明申请

WO2004102216A2 TEST SYSTEMS AND METHODS 审中-公开
标题翻译：测试系统和方法
公开(公告)号：WO2004102216A2
公开(公告)日：2004-11-25
申请号：PCT/US2004/014266
申请日：2004-05-07
申请人： CREDENCE SYSTEMS CORPORATION , SYED, Ahmed, R.
发明人： SYED, Ahmed, R.
IPC分类号： G01R31/00
CPC分类号： G01R31/3191 , G01R31/31922 , G01R31/31928 , G11C29/56 , G11C29/56012 , G11C2029/5606
摘要： The present invention relates to test systems for testing integrated circuit devices. One embodiment of the invention provides a portion of a test system including: on a single CMOS IC, a timing generation circuit; and a formatter coupled to the timing generation circuit. The timing generation circuit generates software words, the formatter receives the software words and provides a specified number of transitions per second and a specified edge placement resolution and accuracy. The formatter includes: a drive circuit and a response circuit. The drive circuit includes a plurality of slices. Each slice receives an independent data stream and produces an independent formatted level. The response circuit includes a plurality of slices. Each slice receives an independent data stream and produces an independent strobe marker.
摘要翻译：本发明涉及用于测试集成电路器件的测试系统。本发明的一个实施例提供了测试系统的一部分，其包括：在单个CMOS IC上，定时产生电路; 以及耦合到定时产生电路的格式器。定时生成电路生成软件字，格式器接收软件字，并提供每秒特定数量的转换和指定的边缘放置分辨率和精度。格式化器包括：驱动电路和响应电路。驱动电路包括多个切片。每个片段接收独立的数据流并产生独立的格式化级别。响应电路包括多个片。每个切片接收独立的数据流并产生独立的选通标记。

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