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1. 发明申请

WO2012030420A2 PACKAGE FOR SYSTEM LEVEL ELECTRONIC PRODUCTS 审中-公开
标题翻译：系统级电子产品包装
公开(公告)号：WO2012030420A2
公开(公告)日：2012-03-08
申请号：PCT/US2011/037905
申请日：2011-05-25
申请人： NATIONAL SEMICONDUCTOR CORPORATION , DARBINYAN, Artur , SINCERBOX, Kurt, E. , CHIN, David, T.
发明人： DARBINYAN, Artur , SINCERBOX, Kurt, E. , CHIN, David, T.
IPC分类号： H05K5/06 , H01L23/02
CPC分类号： H05K5/064
摘要： Methods and arrangements for packaging system level electronics are described. In one aspect, an external skin of the package is formed from isolation paper. In some embodiments, the isolation paper is formed into a box. A printed circuit board is placed within the isolation paper skin and is substantially completely surrounded by a potting material that substantially completely fills the skin. The potting material is cured to solidify the potting material within the isolation paper box and to adhere the potting material to the isolation paper such that the isolation paper forms a skin for a brick of potting material that encapsulates the printed circuit board. The isolation paper skin includes at least one opening that permits an interconnect to be exposed through the skin. With this arrangement, a packaged electronics device is provided and the isolation paper forms the exposed outer surface of the packaged electronics device. The described package is particularly well suited for use in packaging system level power electronics such as power supplies.
摘要翻译：描述了包装系统级电子设备的方法和布置。在一个方面，包装的外部皮肤由隔离纸形成。在一些实施例中，隔离纸被形成为盒子。印刷电路板放置在隔离纸皮肤内，并且基本上完全被基本上完全填充皮肤的灌封材料包围。固化灌封材料以固化隔离纸箱内的灌封材料，并将灌封材料粘附到隔离纸上，使得隔离纸形成封装印刷电路板的灌封材料砖的表皮。隔离纸皮肤包括允许互连通过皮肤暴露的至少一个开口。利用这种布置，提供了封装的电子设备，并且隔离纸形成了封装的电子设备的暴露的外表面。所描述的封装特别适用于封装系统级电力电子设备，如电源。

2. 发明申请

WO2009148768A3 FOIL BASED SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：基于FOIL的半导体封装
公开(公告)号：WO2009148768A3
公开(公告)日：2010-03-04
申请号：PCT/US2009043503
申请日：2009-05-11
申请人： NAT SEMICONDUCTOR CORP , WONG WILL , TU NGHIA THUC , BAYAN JAIME , CHIN DAVID
发明人： WONG WILL , TU NGHIA THUC , BAYAN JAIME , CHIN DAVID
IPC分类号： H01L23/48 , H01L23/495
CPC分类号： H01L23/49582 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/544 , H01L24/29 , H01L24/48 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2221/68345 , H01L2221/68377 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2224/48091 , H01L2224/48247 , H01L2224/83192 , H01L2224/83801 , H01L2224/85001 , H01L2224/85205 , H01L2224/85439 , H01L2224/85455 , H01L2224/85464 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , Y10T29/49121 , Y10T29/49126 , Y10T29/49146 , Y10T29/49156 , Y10T428/12438 , H01L2224/85 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/83205 , H01L2924/00012
摘要： The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, a foil carrier structure is formed by ultrasonically bonding portions of a conductive foil to a metallic carrier. The bonded portions define panels in the foil carrier structure. In some embodiments, the foil carrier structure is cut to form multiple isolated panels that are sealed along their peripheries. Each isolated panel may be approximately the size of a conventional leadframe strip or panel. As a result, existing packaging equipment may be used to add dice, bonding wires and molding material to the panel. The ultrasonic welding helps prevent unwanted substances from penetrating the foil carrier structure during such processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is singulated into integrated circuit packages. Some embodiments relate to methods that utilize some or all of the aforementioned operations. Other embodiments relate to arrangements used in the above processes
摘要翻译：本发明涉及使用薄箔在集成电路封装中形成电互连的方法和布置。在一个实施例中，通过将导电箔的部分超声波结合到金属载体上来形成箔载体结构。接合部分限定箔载体结构中的面板。在一些实施例中，切割箔载体结构以形成沿其周边密封的多个隔离板。每个隔离的面板可以是常规引线框条或面板的尺寸。因此，可以使用现有的包装设备将骰子，接合线和模制材料添加到面板。超声波焊接有助于防止在这种加工步骤期间不需要的物质渗透到铝箔载体结构。在模制的箔载体结构的载体部分被去除之后，将结构分成集成电路封装。一些实施例涉及利用上述操作中的一些或全部的方法。其他实施例涉及上述方法中使用的布置

3. 发明申请

WO2010021776A9 THIN FOIL SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：WO2010021776A9
公开(公告)日：2010-02-25
申请号：PCT/US2009/046000
申请日：2009-06-02
申请人： NATIONAL SEMICONDUCTOR CORPORATION , BAYAN, Jaime, A. , TU, Nghia, Thuc , WONG, Will, Kiang , CHIN, David
发明人： BAYAN, Jaime, A. , TU, Nghia, Thuc , WONG, Will, Kiang , CHIN, David
IPC分类号： H01L23/48 , H01L21/60
摘要： The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.

4. 发明申请

WO2010021776A1 THIN FOIL SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：薄箔半导体封装
公开(公告)号：WO2010021776A1
公开(公告)日：2010-02-25
申请号：PCT/US2009046000
申请日：2009-06-02
申请人： NAT SEMICONDUCTOR CORP , BAYAN JAIME A , TU NGHIA THUC , WONG WILL KIANG , CHIN DAVID
发明人： BAYAN JAIME A , TU NGHIA THUC , WONG WILL KIANG , CHIN DAVID
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L21/4832 , H01L21/4842 , H01L21/568 , H01L23/3107 , H01L23/49517 , H01L23/49582 , H01L24/48 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/85464 , H01L2924/00014 , H01L2924/01046 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , Y10T29/49146 , Y10T29/53174 , Y10T29/53178 , Y10T29/53183 , Y10T29/532 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.
摘要翻译：本发明涉及在集成电路封装中使用薄箔来形成电互连的方法和装置。一种这样的布置涉及箔载体结构，其包括粘附到具有空腔的载体的箔。本发明的一些方法涉及将骰子附接到箔并将箔载体结构封装在模制材料中。在一个实施例中，模制材料压靠箔，这使得箔的一部分膨胀到载体的空腔中。结果，在箔中形成凹凸区域。之后，移除载体，并通过各种技术如研磨来去除箔中的部分凸起区域。该过程有助于限定和电隔离箔中的接触垫。然后将所得的模制箔结构分成多个半导体封装。

5. 发明申请

WO2009148768A2 FOIL BASED SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：基于FOIL的半导体封装
公开(公告)号：WO2009148768A2
公开(公告)日：2009-12-10
申请号：PCT/US2009/043503
申请日：2009-05-11
申请人： NATIONAL SEMICONDUCTOR CORPORATION , WONG, Will , TU, Nghia, Thuc , BAYAN, Jaime , CHIN, David
发明人： WONG, Will , TU, Nghia, Thuc , BAYAN, Jaime , CHIN, David
IPC分类号： H01L23/48 , H01L23/495
CPC分类号： H01L23/49582 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/544 , H01L24/29 , H01L24/48 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2221/68345 , H01L2221/68377 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2224/48091 , H01L2224/48247 , H01L2224/83192 , H01L2224/83801 , H01L2224/85001 , H01L2224/85205 , H01L2224/85439 , H01L2224/85455 , H01L2224/85464 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , Y10T29/49121 , Y10T29/49126 , Y10T29/49146 , Y10T29/49156 , Y10T428/12438 , H01L2224/85 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/83205 , H01L2924/00012
摘要： The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, a foil carrier structure is formed by ultrasonically bonding portions of a conductive foil to a metallic carrier. The bonded portions define panels in the foil carrier structure. In some embodiments, the foil carrier structure is cut to form multiple isolated panels that are sealed along their peripheries. Each isolated panel may be approximately the size of a conventional leadframe strip or panel. As a result, existing packaging equipment may be used to add dice, bonding wires and molding material to the panel. The ultrasonic welding helps prevent unwanted substances from penetrating the foil carrier structure during such processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is singulated into integrated circuit packages. Some embodiments relate to methods that utilize some or all of the aforementioned operations. Other embodiments relate to arrangements used in the above processes
摘要翻译：本发明涉及使用薄箔在集成电路封装中形成电互连的方法和布置。在一个实施例中，通过将导电箔的部分超声波结合到金属载体上来形成箔载体结构。接合部分限定箔载体结构中的面板。在一些实施例中，切割箔载体结构以形成沿其周边密封的多个隔离板。每个隔离的面板可以是常规引线框条或面板的尺寸。因此，可以使用现有的包装设备将骰子，接合线和模制材料添加到面板。超声波焊接有助于防止在这种加工步骤期间不需要的物质渗透到铝箔载体结构。在模制的箔载体结构的载体部分被去除之后，将结构分成集成电路封装。一些实施例涉及利用上述操作中的一些或全部的方法。其他实施例涉及上述方法中使用的布置

6. 发明申请

WO2004022641A2 CALCIUM HYDROXIDE ABSORBENT WITH RHEOLOGY MODIFIER AND PROCESS INVOLVING SAME 审中-公开
标题翻译：具有流变改性剂的氢氧化钙吸收剂和涉及其的方法
公开(公告)号：WO2004022641A2
公开(公告)日：2004-03-18
申请号：PCT/US2003/027830
申请日：2003-09-04
申请人： W.R. GRACE & CO.-CONN , CHIN, David
发明人： CHIN, David
IPC分类号： C08L
CPC分类号： B01J20/041 , B01D53/02 , B01D2257/504 , B01J20/046 , B01J20/22 , B01J20/28004 , B01J20/28016 , B01J20/3007 , B01J2220/42 , B01J2220/46 , B01J2220/49 , Y02C10/08
摘要： Exemplary carbon dioxide absorbent compositions of the invention incorporate calcium hydroxide, water, and a phosphonic acid or salt thereof. The composition is made into a paste and formed into particles that are conveniently and efficiently processable. When hardened, the particles have excellent carbon dioxide absorbent performances, crush resistance, and pore structure.
摘要翻译：本发明的示例性二氧化碳吸收剂组合物包含氢氧化钙，水和膦酸或其盐。将该组合物制成糊状并形成方便且可有效处理的颗粒。当硬化时，颗粒具有优异的二氧化碳吸收性能，抗挤压性和孔隙结构。

7. 发明申请

WO2012030420A3 PACKAGE FOR SYSTEM LEVEL ELECTRONIC PRODUCTS 审中-公开
标题翻译：系统级电子产品包装
公开(公告)号：WO2012030420A3
公开(公告)日：2012-04-26
申请号：PCT/US2011037905
申请日：2011-05-25
申请人： NAT SEMICONDUCTOR CORP , DARBINYAN ARTUR , SINCERBOX KURT E , CHIN DAVID T
发明人： DARBINYAN ARTUR , SINCERBOX KURT E , CHIN DAVID T
IPC分类号： H05K5/06 , H01L23/02
CPC分类号： H05K5/064
摘要： Methods and arrangements for packaging system level electronics are described. In one aspect, an external skin of the package is formed from isolation paper. In some embodiments, the isolation paper is formed into a box. A printed circuit board is placed within the isolation paper skin and is substantially completely surrounded by a potting material that substantially completely fills the skin. The potting material is cured to solidify the potting material within the isolation paper box and to adhere the potting material to the isolation paper such that the isolation paper forms a skin for a brick of potting material that encapsulates the printed circuit board. The isolation paper skin includes at least one opening that permits an interconnect to be exposed through the skin. With this arrangement, a packaged electronics device is provided and the isolation paper forms the exposed outer surface of the packaged electronics device. The described package is particularly well suited for use in packaging system level power electronics such as power supplies.
摘要翻译：描述了包装系统级电子设备的方法和布置。在一个方面，包装的外表皮由隔离纸形成。在一些实施例中，隔离纸形成盒子。印刷电路板被放置在隔离纸皮内并且基本完全被基本上完全填充皮肤的灌封材料包围。灌封材料被固化以固化隔离纸盒内的灌封材料并且将灌封材料粘附到隔离纸上，使得隔离纸形成用于封装印刷电路板的灌封材料砖的表皮。隔离纸表皮包括至少一个允许互连通过皮肤暴露的开口。利用这种布置，提供封装的电子设备，并且隔离纸形成封装的电子设备的暴露的外表面。所描述的封装特别适合用于封装系统级功率电子器件，例如电源。

8. 发明申请

WO2007084496A3 POWER OVER ETHERNET CONTROLLER INTEGRATED CIRCUIT ARCHITECTURE 审中-公开
公开(公告)号：WO2007084496A3
公开(公告)日：2007-07-26
申请号：PCT/US2007/001119
申请日：2007-01-17
申请人： BROADCOM CORPORATION , VORENKAMP, Pieter , WOO, Agnes , TAMMINEEDI, Anil , FUJIMORI, Ichiro , CHIN, David , PERZOW, John
发明人： VORENKAMP, Pieter , WOO, Agnes , TAMMINEEDI, Anil , FUJIMORI, Ichiro , CHIN, David , PERZOW, John
IPC分类号： H04L12/10
摘要： Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. In addition, the PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required. During detection, if the PSE finds the PD to be non-compatible, the PSE can prevent the application of power to that PD device, protecting the PD from possible damage.

9. 发明申请

WO2018145147A1 A METHOD OF TREATING A FIBROTIC CONDITION ASSOCIATED WITH EXCESSIVE COLLAGEN FORMATION USING ACTIVATORS OF THE COLLAGENASE PRODUCTION PATHWAY. 审中-公开
公开(公告)号：WO2018145147A1
公开(公告)日：2018-08-16
申请号：PCT/AU2018/050078
申请日：2018-02-06
申请人： CHIN, David
发明人： CHIN, David
IPC分类号： A61K38/49 , A61K38/36 , A61K38/43 , A61P17/02 , A61P19/04
CPC分类号： A61P17/02 , A61K9/00 , A61K9/0019 , A61K31/573 , A61K31/58 , A61K38/4846 , A61K38/4853 , A61K38/49 , A61K45/06 , A61P19/04 , C12Y304/21031 , C12Y304/21034 , C12Y304/21038 , C12Y304/21068 , A61K2300/00
摘要： The present invention relates to a method of treating a fibrotic disease condition characterized by excessive collagen formation in a subject including a human. The fibrotic disease includes fascial fibromatosis and a keloid scar. The method comprises the administration of an activator of a collagenase pathway such as tissue plasminogen activator (tPA), urokinase plasminogen activator (uPA), kallikrein or Factor XII or a functional analog thereof. If the fibrotic condition is a fascial fibromatosis, the activator is given in combination with a steroid. The present invention is further directed to formulations and protocols for the treatment of fibrotic conditions.

10. 发明申请

WO2012155212A1 METHOD OF TREATING EXCESSIVE COLLAGEN FORMATION 审中-公开
标题翻译：治疗过度胶原蛋白形成的方法
公开(公告)号：WO2012155212A1
公开(公告)日：2012-11-22
申请号：PCT/AU2012/000554
申请日：2012-05-18
申请人： CHIN, David
发明人： CHIN, David
IPC分类号： A61K38/49 , A61P19/04
CPC分类号： A61K38/49
摘要： A treatment for fibromatosis is provided and, particularly, a treatment for palmar and/or plantar fascial fibromatosis is provided. The administration of a plasminogen activator locally to the affected tissue has been found to greatly improve the range of motion to the affected region, to reduce the appearance of the formed cords and nodules and to facilitate easier removal of these structures, if required.
摘要翻译：提供了纤维瘤病的治疗，特别是提供了用于手掌和/或足底筋膜纤维瘤病的治疗。已经发现将纤溶酶原激活剂局部施用于受影响的组织，以大大改善对受影响区域的运动范围，以减少形成的线和结节的外观，并且如果需要，便于去除这些结构。

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