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1. 发明申请

WO2008054678A1 A SEMICONDUCTOR DEVICE COMPRISING NMOS AND PMOS TRANSISTORS WITH EMBEDDED SI/GE MATERIAL FOR CREATING TENSILE AND COMPRESSIVE STRAIN 审中-公开
标题翻译：包含用于创建拉伸和压缩应变的嵌入式SI / GE材料的NMOS和PMOS晶体管的半导体器件
公开(公告)号：WO2008054678A1
公开(公告)日：2008-05-08
申请号：PCT/US2007/022680
申请日：2007-10-26
申请人： ADVANCED MICRO DEVICES INC. , BEYER, Sven , HORSTMANN, Manfred , PRESS, Patrick , BUCHHOLTZ, Wolfgang
发明人： BEYER, Sven , HORSTMANN, Manfred , PRESS, Patrick , BUCHHOLTZ, Wolfgang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： By forming a substantially continuous and uniform semiconductor alloy (107, 207, 307, 407) in one active region (105 A, 205 A, 305 A, 405 A) while patterning the semiconductor alloy (107, 207, 307, 407) in a second active region (105B, 205B, 3O5B, 405B) so as to provide a base semiconductor material (113B, 213B, 313B, 401) in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material (113A, 213A, 313A, 413A), well-established process techniques for forming the gate dielectric (122, 322, 422) may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode (121, 221, 321, 421) may be formed on the basis of the layer (208, 308), which has also been used for defining the central portion (213B, 313B) of the base semiconductor material of one of the active regions (205B, 305B). Hence, by using a single semiconductor alloy (107, 207, 307, 407), the performance of transistors (120A, 120B) of different conductivity types may be individually enhanced.
摘要翻译：通过在将半导体合金（107,207,307,407）图案化的同时在一个有源区（105A，205A，305A，405A）中形成基本上连续且均匀的半导体合金（107,207,307,407）第二有源区域（105B，205B，30B，405B），以便在其中心部分提供基极半导体材料（113B，213B，313B，401），可以诱发不同类型的应变，而在提供相应的基底半导体材料（113A，213A，313A，413A）的覆盖层可以使用用于形成栅极电介质（122,322,422）的完善的工艺技术。在一些说明性实施例中，提供基本上自对准的工艺，其中可以基于层（208,308）形成栅电极（121,221,321,421），其也已经用于限定一个有源区域（205B，305B）的基底半导体材料的中心部分（213B，313B）。因此，通过使用单个半导体合金（107,207,307,407），可以单独提高不同导电类型的晶体管（120A，120B）的性能。

2. 发明申请

WO2006105320A1 HEAT TREATMENT FOR FORMING INTERCONNECT STRUCTURES WITH REDUCED ELECTRO AND STRESS MIGRATION AND/OR RESISTIVITY 审中-公开
标题翻译：用于形成具有降低的电极和应力迁移和/或电阻率的互连结构的热处理
公开(公告)号：WO2006105320A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/011695
申请日：2006-03-30
申请人： ADVANCED MICRO DEVICES, INC. , BUCHHOLTZ, Wolfgang , HETZER, Petra , BUCHHOLTZ, Elvira , PREUSSE, Axel , KEIL, Markus
发明人： BUCHHOLTZ, Wolfgang , HETZER, Petra , BUCHHOLTZ, Elvira , PREUSSE, Axel , KEIL, Markus
IPC分类号： H01L21/768
CPC分类号： H01L21/76886 , H01L21/76883
摘要： By improving the purity of metal lines (112) and/or the crystalline structure, the overall performance of metal lines, especially of highly scaled copper-based semiconductor devices (100) , may be enhanced. The modification of the crystalline structure of the metal lines may be performed by a heat treatment generating locally restricted heating zones, which are scanned along the length direction of the metal lines (112) , and/or a heat treatment comprising a heating step in a vacuum ambient followed by a heating step in a reducing ambient.
摘要翻译：通过提高金属线（112）和/或晶体结构的纯度，可以提高金属线，特别是高规模铜基半导体器件（100）的整体性能。金属线的晶体结构的修改可以通过产生沿着金属线（112）的长度方向扫描的局部限制的加热区域的热处理和/或包括加热步骤的热处理然后在还原环境中进行加热步骤。

3. 发明申请

WO2006007188A1 TECHNIQUE FOR FORMING A SUBSTRATE HAVING CRYSTALLINE SEMICONDUCTOR REGIONS OF DIFFERENT CHARACTERISTICS 审中-公开
标题翻译：形成具有不同特性的晶体半导体区域的衬底的技术
公开(公告)号：WO2006007188A1
公开(公告)日：2006-01-19
申请号：PCT/US2005/018370
申请日：2005-05-25
申请人： ADVANCED MICRO DEVICES, INC. , BUCHHOLTZ, Wolfgang , KRUEGEL, Stephan
发明人： BUCHHOLTZ, Wolfgang , KRUEGEL, Stephan
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/76262 , H01L21/84
摘要： Different types of crystalline semiconductor regions are provided on a single substrate by forming a dielectric region 111 a within a first crystalline semiconductor region 104a. Thereafter, a second crystalline region 152a is positioned above the dielectric region 111 a by wafer bond techniques. In preferred embodiments, isolation structures may be formed in the first crystalline region along with the dielectric region. In particular, crystalline semiconductor regions of different crystallographic orientations may be formed, wherein a high degree of flexibility and compatibility with currently used CMOS processes is maintained.
摘要翻译：通过在第一晶体半导体区域104a内形成电介质区域111a，在单个衬底上提供不同类型的晶体半导体区域。此后，第二结晶区域152a通过晶片接合技术位于电介质区域111a的上方。在优选实施例中，隔离结构可以与电介质区一起形成在第一晶体区域中。特别地，可以形成不同晶体取向的晶体半导体区域，其中保持了高度的灵活性和与当前使用的CMOS工艺的兼容性。

4. 发明申请

WO2005017992A1 FIELD EFFECT TRANSISTOR HAVING A DOPED GATE ELECTRODE WITH REDUCED GATE DEPLETION AND METHOD OF FORMING THE TRANSISTOR 审中-公开
标题翻译：具有降低门极截面的多孔栅电极的场效应晶体管和形成晶体管的方法
公开(公告)号：WO2005017992A1
公开(公告)日：2005-02-24
申请号：PCT/US2004/017705
申请日：2004-06-04
申请人： ADVANCED MICRO DEVICES, INC. , WIECZOREK, Karsten , FEUDEL, Thomas , KAMMLER, Thorsten , BUCHHOLTZ, Wolfgang
发明人： WIECZOREK, Karsten , FEUDEL, Thomas , KAMMLER, Thorsten , BUCHHOLTZ, Wolfgang
IPC分类号： H01L21/336
CPC分类号： H01L29/66553 , H01L29/4908 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/78618
摘要： By forming an implantation mask (220) prior to the definition of the drain and the source areas (208), an effective decoupling of the gate dopant concentration from that of the drain and source concentrations is achieved. Moreover, after removal of the implantation mask (220), the lateral dimension of the gate electrode (205) may be defined by well-established sidewall spacer (207) techniques, thereby providing a scaling advantage with respect to conventional approaches based on photolithography and anisotropic etching.
摘要翻译：通过在漏极和源极区域（208）的定义之前形成注入掩模（220），实现了栅极掺杂剂浓度与漏极和源极浓度的有效去耦。此外，在移除注入掩模（220）之后，栅电极（205）的横向尺寸可以通过确定的侧壁间隔物（207）技术来限定，从而相对于基于光刻的常规方法提供缩放优点，各向异性蚀刻。

5. 发明申请

WO2006049834A1 A SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR REGIONS HAVING DIFFERENTLY STRAINED CHANNEL REGIONS AND A METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：包括具有不同应变通道区域的半导体区域的半导体器件及其制造方法
公开(公告)号：WO2006049834A1
公开(公告)日：2006-05-11
申请号：PCT/US2005/036779
申请日：2005-10-12
申请人： ADVANCED MICRO DEVICES, INC. , HORSTMANN, Manfred , PRUEFER, Ekkehard , BUCHHOLTZ, Wolfgang
发明人： HORSTMANN, Manfred , PRUEFER, Ekkehard , BUCHHOLTZ, Wolfgang
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/265 , H01L21/26506 , H01L21/823807 , H01L21/84 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the charge carrier mobility of different transistor elements may individually be adjusted. In particular, in in-laid gate structure transistor architecture, NMOS transistors and PMOS transistors may receive a tensile and a compressive stress, respectively.
摘要翻译：通过局部改变根据叠层栅极技术形成的晶体管配置的横向包围栅电极结构的电介质层的固有应力，可以单独地调节不同晶体管元件的电荷载流子迁移率。特别地，在嵌入式栅结构晶体管架构中，NMOS晶体管和PMOS晶体管可以分别接收拉伸和压缩应力。

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