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1. 发明申请

WO2007002695A2 LAYOUT MODIFICATION TO ELIMINATE LINE BENDING CAUSED BY LINE MATERIAL SHRINKAGE 审中-公开
标题翻译：消除由线材收缩引起的线弯曲的布局修改
公开(公告)号：WO2007002695A2
公开(公告)日：2007-01-04
申请号：PCT/US2006/025031
申请日：2006-06-26
申请人： TEXAS INSTRUMENTS INCORPORATED , UKRAINTSEV, Vladimir, Alexeevich , MASON, Mark, E. , BLATCHFORD, James, Walter , SMITH, Brian, Ashley , HORNUNG, Brian, Edward , ANDERSON, Dirk, Noel
发明人： UKRAINTSEV, Vladimir, Alexeevich , MASON, Mark, E. , BLATCHFORD, James, Walter , SMITH, Brian, Ashley , HORNUNG, Brian, Edward , ANDERSON, Dirk, Noel
IPC分类号： H01L23/58 , H01L21/302
CPC分类号： G03F7/70425 , H01L21/0273
摘要： A semiconductor device and a method for fabricating a semiconductor device with reduced line bending is provided. The method can include forming a first layer and depositing a photoresist layer on the first layer. The photoresist layer can be patterned, such that the patterning comprises at least one support feature (271) disposed adjacent to an outside of a corner feature (250).
摘要翻译：提供一种半导体器件和用于制造具有减少的线弯曲的半导体器件的方法。该方法可以包括形成第一层并在第一层上沉积光致抗蚀剂层。光致抗蚀剂层可以被图案化，使得图案化包括邻近角部特征（250）的外部设置的至少一个支撑特征（271）。

2. 发明申请

WO2012119098A2 PATTERN-SPLIT DECOMPOSITION STRATEGY FOR DOUBLE-PATTERNED LITHOGRAPHY PROCESS 审中-公开
标题翻译：双图形光刻工艺的分形分解策略
公开(公告)号：WO2012119098A2
公开(公告)日：2012-09-07
申请号：PCT/US2012/027534
申请日：2012-03-02
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , BLATCHFORD, James, Walter
发明人： BLATCHFORD, James, Walter
IPC分类号： H01L21/027
CPC分类号： H01L21/32139 , H01L21/31144 , H01L21/76816 , H01L21/76838 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may be formed by a process of forming a first interconnect pattern (208) in a plurality of parallel route tracks (206), and forming a second interconnect pattern (224) in the plurality of parallel route tracks. The first interconnect pattern (208) includes a first lead pattern which extends to a first point (216) in an instance of the first plurality of parallel route tracks, and the second interconnect pattern (224) includes a second lead pattern which extends to a second point (232) in the same instance of the plurality of parallel route tracks, such that the second point (232) is laterally separated from the first point (216) by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern.
摘要翻译：集成电路可以通过在多个平行路径轨道（206）中形成第一互连图案（208）并且在多个平行路径轨道（206）中形成第二互连图案（224）平行路线轨道。第一互连图案（208）包括在第一多个平行路径轨迹的实例中延伸到第一点（216）的第一引线图案，并且第二互连图案（224）包括第二引线图案，该第二引线图案延伸到所述第二点（232）在所述多个平行路径轨迹的相同情况下，使得所述第二点（232）与所述第一点（216）横向分开相邻的相邻空间之间的距离的一倍至一倍半的距离平行引线图案在多个平行路线轨迹中。执行形成由第一互连图案和第二互连图案限定的互连级中的金属互连线的金属互连形成工艺。

3. 发明申请

WO2007002695A3 LAYOUT MODIFICATION TO ELIMINATE LINE BENDING CAUSED BY LINE MATERIAL SHRINKAGE 审中-公开
标题翻译：布局修改消除由线材收缩引起的弯曲
公开(公告)号：WO2007002695A3
公开(公告)日：2007-03-15
申请号：PCT/US2006025031
申请日：2006-06-26
申请人： TEXAS INSTRUMENTS INC , UKRAINTSEV VLADIMIR ALEXEEVICH , MASON MARK E , BLATCHFORD JAMES WALTER , SMITH BRIAN ASHLEY , HORNUNG BRIAN EDWARD , ANDERSON DIRK NOEL
发明人： UKRAINTSEV VLADIMIR ALEXEEVICH , MASON MARK E , BLATCHFORD JAMES WALTER , SMITH BRIAN ASHLEY , HORNUNG BRIAN EDWARD , ANDERSON DIRK NOEL
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： G03F7/70425 , H01L21/0273
摘要： A semiconductor device and a method for fabricating a semiconductor device with reduced line bending is provided. The method can include forming a first layer and depositing a photoresist layer on the first layer. The photoresist layer can be patterned, such that the patterning comprises at least one support feature (271) disposed adjacent to an outside of a corner feature (250).
摘要翻译：提供了一种半导体器件和用于制造具有减少的线弯曲的半导体器件的方法。该方法可以包括形成第一层并且在第一层上沉积光致抗蚀剂层。光致抗蚀剂层可以被图案化，使得图案化包括设置在角部件（250）的外侧附近的至少一个支撑部件（271）。

4. 发明申请

WO2012119105A3 HYBRID PITCH-SPLIT PATTERN-SPLIT LITROGRAPHY PROCESS 审中-公开
标题翻译：混合分选分割图案分析方法
公开(公告)号：WO2012119105A3
公开(公告)日：2012-11-15
申请号：PCT/US2012027554
申请日：2012-03-02
申请人： TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN , BLATCHFORD JAMES WALTER
发明人： BLATCHFORD JAMES WALTER
IPC分类号： H01L21/027
CPC分类号： H01L21/32139 , H01L21/31144 , H01L21/76816 , H01L21/76838 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks (206), using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks (206). The first interconnect pattern (208) includes a first lead pattern (212) which extends to a first point. The second interconnect pattern (220) includes a second lead pattern (224) which is parallel to and immediately adjacent to the first lead pattern (212). The third interconnect pattern (23) includes a third lead pattern (234) which is parallel to and immediately adjacent to the second lead pattern (224) and which extends to a second point (236) in the first instance of the parallel route tracks, laterally separated from the first point (214) by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.
摘要翻译：集成电路可以通过使用光刻处理形成多个平行路径轨道（206）中的三个互连图案的过程来形成，该光刻处理具有能够将间距距离为平行路径轨道（206）的间距距离的两倍的照明源，。第一互连图案（208）包括延伸到第一点的第一引线图案（212）。第二互连图案（220）包括与第一引线图案（212）平行并且紧邻第一引线图案（212）的第二引线图案（224）。第三互连图案（23）包括第三引线图案（234），其平行于并且紧邻第二引线图案（224），并且在第一平行路径轨迹中延伸到第二点（236）与第一点（214）横向分开距离小于平行路径轨迹中相邻图案之间的空间的一倍半。

5. 发明申请

WO2012119098A3 PATTERN-SPLIT DECOMPOSITION STRATEGY FOR DOUBLE-PATTERNED LITHOGRAPHY PROCESS 审中-公开
标题翻译：用于双模式平移过程的分形分解策略
公开(公告)号：WO2012119098A3
公开(公告)日：2012-11-08
申请号：PCT/US2012027534
申请日：2012-03-02
申请人： TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN , BLATCHFORD JAMES WALTER
发明人： BLATCHFORD JAMES WALTER
IPC分类号： H01L21/027
CPC分类号： H01L21/32139 , H01L21/31144 , H01L21/76816 , H01L21/76838 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may be formed by a process of forming a first interconnect pattern (208) in a plurality of parallel route tracks (206), and forming a second interconnect pattern (224) in the plurality of parallel route tracks. The first interconnect pattern (208) includes a first lead pattern which extends to a first point (216) in an instance of the first plurality of parallel route tracks, and the second interconnect pattern (224) includes a second lead pattern which extends to a second point (232) in the same instance of the plurality of parallel route tracks, such that the second point (232) is laterally separated from the first point (216) by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern.
摘要翻译：可以通过在多个平行路径轨道（206）中形成第一互连图案（208）并在多条平行路径轨道中形成第二互连图案（224）的过程来形成集成电路。第一互连图案（208）包括在第一多个并行路径轨道的情况下延伸到第一点（216）的第一引线图案，并且第二互连图案（224）包括第二引线图案，其延伸到在多个平行路径轨道的相同实例中的第二点（232），使得第二点（232）与第一点（216）横向分离一段距离，相邻多个平行路径轨道中的平行引线图案。执行金属互连形成工艺，其形成由第一互连图案和第二互连图案限定的互连层中的金属互连线。

6. 发明申请

WO2012119105A2 HYBRID PITCH-SPLIT PATTERN-SPLIT LITROGRAPHY PROCESS 审中-公开
标题翻译：混合间距分割模式分裂图像处理
公开(公告)号：WO2012119105A2
公开(公告)日：2012-09-07
申请号：PCT/US2012/027554
申请日：2012-03-02
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , BLATCHFORD, James, Walter
发明人： BLATCHFORD, James, Walter
IPC分类号： H01L21/027
CPC分类号： H01L21/32139 , H01L21/31144 , H01L21/76816 , H01L21/76838 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks (206), using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks (206). The first interconnect pattern (208) includes a first lead pattern (212) which extends to a first point. The second interconnect pattern (220) includes a second lead pattern (224) which is parallel to and immediately adjacent to the first lead pattern (212). The third interconnect pattern (23) includes a third lead pattern (234) which is parallel to and immediately adjacent to the second lead pattern (224) and which extends to a second point (236) in the first instance of the parallel route tracks, laterally separated from the first point (214) by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.
摘要翻译：集成电路可以通过以下处理形成：使用具有照明源的光刻工艺在多个平行路径轨道（206）中形成三个互连图案，所述照明源能够具有节距间距的两倍平行路线轨迹（206）。第一互连图案（208）包括延伸到第一点的第一引线图案（212）。第二互连图案（220）包括与第一引线图案（212）平行且紧邻的第二引线图案（224）。第三互连图案（23）包括第三引线图案（234），该第三引线图案与第二引线图案（224）平行且紧邻，并且在平行路线轨道的第一实例中延伸至第二点（236）与第一点（214）横向分开的距离小于平行路径轨道中相邻图案之间间隔的一倍半。

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