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1. 发明申请

WO2005013495A3 SPACE EFFICIENT LOW POWER CYCLIC A/D CONVERTER 审中-公开
标题翻译：空间高效低功耗循环A / D转换器
公开(公告)号：WO2005013495A3
公开(公告)日：2005-06-09
申请号：PCT/US2004022511
申请日：2004-07-15
申请人： FREESCALE SEMICONDUCTOR INC , ATRISS AHMAD H , ALLEN STEVEN P
发明人： ATRISS AHMAD H , ALLEN STEVEN P
IPC分类号： H03M1/06 , H03M1/34 , H03M1/40 , H04B20060101
CPC分类号： H03M1/0695 , H03M1/40
摘要： Methods and apparatus are provided for an analog converter (60). The apparatus comprises a first redundant signed digit (RSD) stage (62) and a configurable block (61). The configurable block (61) converts to a sample/hold circuit to sample a single ended analog signal. The sampled signal is then scaled, converted to a differential signal and provided to the first RSD stage (62). The first RSD stage (62) outputs a bit value corresponding to the magnitude of the digital signal. In a next half clock cycle the first RSD stage (62) calculates a residue that is provided to the configurable block (61). The configurable block (61) is converted to a second redundant signed digit stage and generates a bit value corresponding to the magnitude of the residue provided by the first RSD stage. The first and second RSD stages cycle back and forth generating logic value each half clock cycle until the desired bit resolution is achieved. The configurable block (61) is then converted back to a sample/hold circuit to start another conversion process.
摘要翻译：提供了用于模拟转换器（60）的方法和装置。该装置包括第一冗余有符号数字（RSD）级（62）和可配置块（61）。可配置模块（61）转换为采样/保持电路以采样单端模拟信号。然后对采样的信号进行缩放，转换成差分信号并提供给第一RSD级（62）。第一RSD级（62）输出对应于数字信号大小的比特值。在下一个半时钟周期中，第一RSD级（62）计算提供给可配置块（61）的余量。可配置块（61）被转换成第二冗余有符号数位级，并且生成与由第一RSD级提供的残留量相对应的比特值。第一和第二RSD级每半个时钟周期前后循环产生逻辑值，直到达到期望的位分辨率。然后可配置模块（61）被转换回采样/保持电路以开始另一个转换过程。

2. 发明申请

WO2005013495A2 SPACE EFFICIENT LOW POWER CYCLIC A/D CONVERTER 审中-公开
标题翻译：空间效率低功率循环A / D转换器
公开(公告)号：WO2005013495A2
公开(公告)日：2005-02-10
申请号：PCT/US2004/022511
申请日：2004-07-15
申请人： FREESCALE SEMICONDUCTOR, INC. , ATRISS, Ahmad, H. , ALLEN, Steven, P.
发明人： ATRISS, Ahmad, H. , ALLEN, Steven, P.
IPC分类号： H04B
CPC分类号： H03M1/0695 , H03M1/40
摘要： Methods and apparatus are provided for an analog converter (60). The apparatus comprises a first redundant signed digit (RSD) stage (62) and a configurable block (61). The configurable block (61) converts to a sample/hold circuit to sample a single ended analog signal. The sampled signal is then scaled, converted to a differential signal and provided to the first RSD stage (62). The first RSD stage (62) outputs a bit value corresponding to the magnitude of the digital signal. In a next half clock cycle the first RSD stage (62) calculates a residue that is provided to the configurable block (61). The configurable block (61) is converted to a second redundant signed digit stage and generates a bit value corresponding to the magnitude of the residue provided by the first RSD stage. The first and second RSD stages cycle back and forth generating logic value each half clock cycle until the desired bit resolution is achieved. The configurable block (61) is then converted back to a sample/hold circuit to start another conversion process.
摘要翻译：为模拟转换器（60）提供了方法和装置。该装置包括第一冗余有符号位（RSD）级（62）和可配置块（61）。可配置块（61）转换为采样/保持电路以对单端模拟信号进行采样。然后将采样的信号进行比例缩放，转换成差分信号并提供给第一RSD级（62）。第一RSD级（62）输出与数字信号的幅度对应的位值。在下一个半时钟周期中，第一RSD级（62）计算提供给可配置块（61）的残差。可配置块（61）被转换为第二冗余有符号数字级，并且产生对应于由第一RSD级提供的残差幅度的位值。第一和第二RSD级每个半时钟周期来回循环产生逻辑值，直到达到所需的位分辨率。然后将可配置块（61）转换回采样/保持电路以开始另一转换处理。

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