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1. 发明申请

WO2012012070A1 VOLTAGE SENSITIVE RESISTOR (VSR) READ ONLY MEMORY 审中-公开
标题翻译：电压敏感电阻（VSR）只读存储器
公开(公告)号：WO2012012070A1
公开(公告)日：2012-01-26
申请号：PCT/US2011/041273
申请日：2011-06-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： KANE, Terence, L. , WANG, Yun-Yu , WONG, Keith Kwong, Hon
IPC分类号： H01C7/00 , H01C7/10
CPC分类号： H01L45/1616 , G11C17/14 , H01C7/1013 , H01C7/105 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a voltage sensitive resistor (VSR) write once (WO) read only memory (ROM) device which includes a semiconductor device and a VSR connected, to die semiconductor device. The VSR WO ROM device is a write once read only device. The VSR includes a CVD titanium nitride layer having residual titanium-carbon bonding such that the VSR is resistive as formed and can become less resistive by an order of 10 2 , more preferably 10 3 and most preferably 10 4 when a predetermined voltage and current are applied to the VSR. A plurality of the VSR WO ROM devices may be arranged to form a high density programmable logic circuit in a 3-D stack. Also disclosed are methods to form the VSR WO ROM device.
摘要翻译：公开了一种包括半导体器件和VSR连接的一次电压敏感电阻（VSR）一次写入（WO）只读存储器（ROM）器件，用于裸片半导体器件。 VSR WO ROM设备是一次写入只读设备。 VSR包括具有残留的钛 - 碳键合的CVD氮化钛层，使得VSR是形成的电阻的，并且当预定的电压和电流施加到该电极时，可以变得更小的电阻值为102，更优选为103，最优选为104。 VSR。多个VSR WO ROM器件可以被布置成在3-D堆叠中形成高密度可编程逻辑电路。还公开了形成VSR WO ROM器件的方法。

2. 发明申请

WO2006063060A2 DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS 审中-公开
标题翻译：具有增强应力状态的装置及相关方法
公开(公告)号：WO2006063060A2
公开(公告)日：2006-06-15
申请号：PCT/US2005/044281
申请日：2005-12-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHIDAMBARRAO, Dureseti , LI, Ying , MALIK, Rajeev , NARASIMHA, Shreesh , YANG, Haining , ZHU, Huilong
发明人： CHIDAMBARRAO, Dureseti , LI, Ying , MALIK, Rajeev , NARASIMHA, Shreesh , YANG, Haining , ZHU, Huilong
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译：本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：向所述器件施加第一氮化硅衬垫并施加与所述快速氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

3. 发明申请

WO2005067539A3 MULTILAYER CERAMIC SUBSTRATE WITH SINGLE VIA ANCHORED PAD AND METHOD OF FORMING 审中-公开
公开(公告)号：WO2005067539A3
公开(公告)日：2005-07-28
申请号：PCT/US2005/001367
申请日：2005-01-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , REDDY, Srinivasa, N. , FAROOQ, Mukta, G. , PRETTYMAN, Kevin, M.
发明人： REDDY, Srinivasa, N. , FAROOQ, Mukta, G. , PRETTYMAN, Kevin, M.
IPC分类号： H01L23/06
摘要： A multilayer ceramic substrate in which an outer metal pad is anchored to the substrate by a single metal-filled via in the first ceramic layer adjacent to the metal pad. In turn, this single metal-filled via is anchored to the substrate by a larger, single metal-filled, via in the next ceramic layer adjacent to the first ceramic layer. Preferably, the metal filled vies and metal pad are 100 volume percent metal.

4. 发明申请

WO2013006531A1 4-TERMINAL PIEZOELECTRONIC TRANSISTOR (PET) 审中-公开
标题翻译： 4端子电子晶体管（PET）
公开(公告)号：WO2013006531A1
公开(公告)日：2013-01-10
申请号：PCT/US2012/045197
申请日：2012-07-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ELMEGREEN, Bruce, G. , MARTYNA, Glenn, J. , NEWNS, Dennis, M. , ROSSNAGEL, Stephen, M. , SOLOMON, Paul, M.
发明人： ELMEGREEN, Bruce, G. , MARTYNA, Glenn, J. , NEWNS, Dennis, M. , ROSSNAGEL, Stephen, M. , SOLOMON, Paul, M.
IPC分类号： H01L41/00
CPC分类号： H01L49/00 , H01L2224/04105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , Y10T29/42
摘要： A 4-terminal piezoelectronic transistor (PET) which includes a piezoelectric (PE) material disposed between first and second electrodes; an insulator material disposed on the second electrode; a third electrode disposed on the insulator material and a piezoresistive (PR) material disposed between the third electrode and a fourth electrode. An applied voltage across the first and second electrodes causing a pressure from the PE material to be applied to the PR material through the insulator material, the electrical resistance of the PR material being dependent upon the pressure applied by the PE material. The first and second electrodes are electrically isolated from the third and fourth electrodes. Also disclosed are logic devices fabricated from 4-terminal PETs and a method of fabricating a 4-terminal PET.
摘要翻译： 4端子压电晶体管（PET），其包括设置在第一和第二电极之间的压电（PE）材料; 设置在所述第二电极上的绝缘体材料; 设置在绝缘体材料上的第三电极和设置在第三电极和第四电极之间的压阻（PR）材料。在第一和第二电极两端施加的电压导致来自PE材料的压力通过绝缘体材料施加到PR材料上，PR材料的电阻取决于PE材料施加的压力。第一和第二电极与第三和第四电极电隔离。还公开了由4端子PET制造的逻辑器件和制造4端子PET的方法。

5. 发明申请

WO2012128956A1 NITRIDE GATE DIELECTRIC FOR GRAPHENE MOSFET 审中-公开
标题翻译：用于石墨MOSFET的氮化物电介质
公开(公告)号：WO2012128956A1
公开(公告)日：2012-09-27
申请号：PCT/US2012/028172
申请日：2012-03-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： AVOURIS, Phaedon , NEUMAYER, Deborah, A. , ZHU, Wenjuan
IPC分类号： B32B9/00 , H01L21/04
CPC分类号： H01L29/518 , H01L29/1606 , H01L29/42384 , H01L29/4908 , H01L29/78684
摘要： A semiconductor structure which includes a substrate; a graphene layer on the substrate; a source electrode and a drain electrode on the graphene layer, the source electrode and drain electrode being spaced apart by a predetermined dimension; a nitride layer on the graphene layer between the source electrode and drain electrode; and a gate electrode on the nitride layer, wherein the nitride layer is a gate dielectric for the gate electrode.
摘要翻译：一种包括衬底的半导体结构; 基板上的石墨烯层; 在石墨烯层上的源电极和漏电极，源电极和漏极间隔开预定尺寸; 在源电极和漏电极之间的石墨烯层上的氮化物层; 以及氮化物层上的栅极电极，其中氮化物层是用于栅电极的栅极电介质。

6. 发明申请

WO2003040887A3 AUTOMATED INFORMATION TECHNOLOGY MANAGEMENT SYSTEM 审中-公开
公开(公告)号：WO2003040887A3
公开(公告)日：2003-05-15
申请号：PCT/US2002/035713
申请日：2002-11-06
申请人： INTERNATIONAL BUSINESS MACHINES COPORATION
发明人： ERNEST, Mark, L. , FINDEN-BROWNE, Christopher , MOORE, James, R.
IPC分类号： G06F17/60
摘要： System and process for managing an IT infrastructure which collects transaction information on a component basis. The transaction data is used to evaluate the contribution of each component of the system as well as the business value of the service, and for the infrastructure as a whole. The usage data is prepared as reports and used in an IT management workflow model to make decisions about such things as the timing of system upgrades, strategic architectural decisions, timing of sunsetting of service components, both hardware and software, and the return-on-investment (ROI) valuation of IT investments. Component values may be assessed on either a volume (number of transactions) basis, or on the discrete dollar value of the transactions supported by the component.

7. 发明申请

WO2003040887A2 AUTOMATED INFORMATION TECHNOLOGY MANAGEMENT SYSTEM 审中-公开
标题翻译：自动化信息技术管理系统
公开(公告)号：WO2003040887A2
公开(公告)日：2003-05-15
申请号：PCT/US2002/035713
申请日：2002-11-06
申请人： INTERNATIONAL BUSINESS MACHINES COPORATION
发明人： ERNEST, Mark, L. , FINDEN-BROWNE, Christopher , MOORE, James, R.
IPC分类号： G06F
CPC分类号： G06Q10/10 , G06F11/3476 , G06Q10/063
摘要： System and process for managing an IT infrastructure which collects transaction information on a component basis. The transaction data is used to evaluate the contribution of each component of the system as well as the business value of the service, and for the infrastructure as a whole. The usage data is prepared as reports and used in an IT management workflow model to make decisions about such things as the timing of system upgrades, strategic architectural decisions, timing of sunsetting of service components, both hardware and software, and the return-on-investment (ROI) valuation of IT investments. Component values may be assessed on either a volume (number of transactions) basis, or on the discrete dollar value of the transactions supported by the component.
摘要翻译：用于管理基于组件收集交易信息的IT基础架构的系统和流程。交易数据用于评估系统的每个组成部分的贡献以及服务的业务价值以及整个基础设施。使用数据作为报告准备，并用于IT管理工作流模型，以便对系统升级的时间安排，战略架构决策，服务组件的停机时间，硬件和软件以及退货时间等做出决定。 IT投资的投资（ROI）估值。组件值可以以卷（交易数量）为基础，或由组件支持的交易的离散美元价值进行评估。

8. 发明申请

WO2012151157A1 TRANSPARENT PHOTODETECTOR 审中-公开
标题翻译：透明光电转换器
公开(公告)号：WO2012151157A1
公开(公告)日：2012-11-08
申请号：PCT/US2012/035816
申请日：2012-04-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BARWICZ, Tymon
发明人： BARWICZ, Tymon
IPC分类号： H01L27/148
CPC分类号： G01J1/42
摘要： A transparent photodetector. The transparent photodetector includes a substrate; a waveguide on the substrate; a displaceable structure that can be displaced with respect to the substrate, the displaceable structure in proximity to the waveguide; and a silicon nanowire array suspended with respect to the substrate and mechanically linked to the displaceable structure, the silicon nanowire array comprising a plurality of silicon nanowires having piezoresistance. In operation, a light source propagating through the waveguide results in an optical force on the displaceable structure which further results in a strain on the nanowires to cause a change in electrical resistance of the nanowires. The substrate may be a semiconductor on insulator substrate.
摘要翻译：透明光电探测器。透明光电检测器包括基板; 衬底上的波导; 可移位的结构，其可以相对于衬底移位，靠近波导的位移结构; 以及相对于衬底悬挂并机械地连接到可位移结构的硅纳米线阵列，所述硅纳米线阵列包括具有压阻的多个硅纳米线。在操作中，通过波导传播的光源导致可移动结构上的光学力，这进一步导致纳米线上的应变导致纳米线的电阻变化。衬底可以是绝缘体上的半导体衬底。

9. 发明申请

WO2012103033A1 FINFET STRUCTURE HAVING FULLY SILICIDED FINS 审中-公开
标题翻译：具有完全硅化物的FINFET结构
公开(公告)号：WO2012103033A1
公开(公告)日：2012-08-02
申请号：PCT/US2012/022264
申请日：2012-01-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BRYANT, Andres , BU, Huiming , GUO, Dechao , HAENSCH, Wilfried, E. , YEH, Chun-chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L21/28518 , H01L21/76895 , H01L29/66795 , H01L29/7843 , H01L29/785
摘要： A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.
摘要翻译：一种半导体器件，其包括形成在半导体衬底上的半导体材料的散热片，然后形成在鳍上并与翅片接触的栅电极。在栅极电极和鳍片上沉积绝缘体层。然后在绝缘体层中蚀刻沟槽开口。沟槽开口暴露翅片并在翅片之间延伸。然后将鳍片通过沟槽开口硅化。然后，沟槽开口填充有与硅化物翅片接触的金属，以形成连接散热片的局部互连。

10. 发明申请

WO2010059546A1 AUTHENTICATION OF BRAND NAME PRODUCT OWNERSHIP USING PUBLIC KEY CRYPTOGRAPHY 审中-公开
标题翻译：品牌名称产品的认证使用公开的关键字符
公开(公告)号：WO2010059546A1
公开(公告)日：2010-05-27
申请号：PCT/US2009/064529
申请日：2009-11-16
申请人： POLONSKY, Katerina , POLONSKY, Vladimir
发明人： POLONSKY, Katerina , POLONSKY, Vladimir
IPC分类号： H04L9/32
CPC分类号： H04L9/3247 , H04L2209/56 , H04L2209/805
摘要： Disclosed is a method of using public key cryptography to determine the authenticity of a brand name product. The brand name product has a unique message personal to the owner of the brand name product and a digital signature which includes at least the encrypted unique personal message. The unique message and digital signature are authenticated using a public key.
摘要翻译：公开了一种使用公钥密码术来确定品牌产品的真实性的方法。品牌产品对品牌产品的所有者和至少包含加密的独特个人消息的数字签名具有唯一的消息。使用公钥对独特的消息和数字签名进行身份验证。

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