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1. 发明申请

WO2012103033A1 FINFET STRUCTURE HAVING FULLY SILICIDED FINS 审中-公开
标题翻译：具有完全硅化物的FINFET结构
公开(公告)号：WO2012103033A1
公开(公告)日：2012-08-02
申请号：PCT/US2012/022264
申请日：2012-01-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BRYANT, Andres , BU, Huiming , GUO, Dechao , HAENSCH, Wilfried, E. , YEH, Chun-chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L21/28518 , H01L21/76895 , H01L29/66795 , H01L29/7843 , H01L29/785
摘要： A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.
摘要翻译：一种半导体器件，其包括形成在半导体衬底上的半导体材料的散热片，然后形成在鳍上并与翅片接触的栅电极。在栅极电极和鳍片上沉积绝缘体层。然后在绝缘体层中蚀刻沟槽开口。沟槽开口暴露翅片并在翅片之间延伸。然后将鳍片通过沟槽开口硅化。然后，沟槽开口填充有与硅化物翅片接触的金属，以形成连接散热片的局部互连。

2. 发明申请

WO2013101790A2 FINFET WITH MERGED FINS AND VERTICAL SILICIDE 审中-公开
标题翻译：具有合并的FINS和垂直硅胶的FINFET
公开(公告)号：WO2013101790A2
公开(公告)日：2013-07-04
申请号：PCT/US2012/071579
申请日：2012-12-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BRYANT, Andres , BASKER, Veeraraghavan, S. , BU, Huiming , HAENSCH, Wilfried , LEOBANDUNG, Effendi , LIN, Chung-hsun , STANDAERT, Theordorus, E. , YAMASHITA, Tenko , YEH, Chun-chen
IPC分类号： H01L27/12 , H01L21/336 , H01L29/78
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了一种用于制造finFET器件的方法。翅片结构形成在BOX层上。翅片结构包括半导体层并沿第一方向延伸。栅极叠层形成在鳍状结构上的BOX层上并沿第二方向延伸。栅极堆叠包括高K电介质层和金属栅极。栅极间隔物形成在栅极堆叠的侧壁上，并且沉积外延层以使翅片结构合并。植入离子以形成源极和漏极区，并且在栅极间隔物的侧壁上形成虚设间隔物。虚拟间隔物用作掩模以凹进或完全去除外延层的暴露部分。硅化形成邻接源极和漏极区域的硅化物区域，并且每个都包括位于源极或漏极区域的垂直侧壁上的垂直部分。

3. 发明申请

WO2015099862A1 METHOD AND STRUCTURE FOR MULTIGATE FINFET DEVICE EPI-EXTENSION JUNCTION CONTROL BY HYDROGEN TREATMENT 审中-公开
标题翻译：通过氢处理方法和结构方法和多结构FinFET器件EPI-EXTENSION JUNCTION控制
公开(公告)号：WO2015099862A1
公开(公告)日：2015-07-02
申请号：PCT/US2014/060000
申请日：2014-10-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BASKER, Veeraraghavan S. , LIU, Zuoguang , YAMASHITA, Tenko , YEH, Chun-chen
IPC分类号： H01L21/336 , H01L29/78 , H01L21/20
CPC分类号： H01L29/785 , H01L21/02694 , H01L29/66742 , H01L29/66795 , H01L29/66818
摘要： Embodiments are directed to forming a structure comprising at least one fin, a gate, and a spacer, applying an annealing process to the structure to create a gap between the at least one fin and the spacer, and growing an epitaxial semiconductor layer in the gap between the spacer and the at least one fin.
摘要翻译：实施例涉及形成包括至少一个翅片，栅极和间隔物的结构，向该结构施加退火工艺以在该至少一个翅片和间隔物之间产生间隙，以及在间隙中生长外延半导体层在间隔件和至少一个翅片之间。

4. 发明申请

WO2014089438A1 COMPOSITE HARDMASK FOR FINFET STRUCTURES 审中-公开
标题翻译： FINFET结构的复合复合材料
公开(公告)号：WO2014089438A1
公开(公告)日：2014-06-12
申请号：PCT/US2013/073590
申请日：2013-12-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BASKER, Veeraraghavan, S. , LEOBANDUNG, Effendi , YAMASHITA, Tenko , YEH, Chun-chen
IPC分类号： H01L29/772 , H01L21/033 , H01L21/308
CPC分类号： H01L29/785 , H01L29/66795
摘要： A FinFET structure is formed by forming a hardmask layer on a substrate including a silicon-containing layer on an insulating layer. The hardmask layer includes first, second and third layers on the silicon-containing layer. An array of fins is formed from the hardmask layer and the silicon-containing layer. A gate is formed covering a portion but not all of a length of each of the array of fins. The portion covers each of the fins in the array. The gate defines source/drain regions on either side of the gate. A spacer is formed on each side of the gate, the forming of the spacer performed to remove the third layer from portions of the fins in the source/drain regions. The second layer of the hardmask layer is removed from the portions of the fins in the source/drain regions, and the fins in the source/drain regions are merged.
摘要翻译：通过在绝缘层上包含含硅层的衬底上形成硬掩模层来形成FinFET结构。硬掩模层包括含硅层上的第一层，第二层和第三层。翅片阵列由硬掩模层和含硅层形成。形成盖子，其覆盖翅片阵列中的每一个的一部分而不是全部长度。该部分覆盖阵列中的每个翅片。门限定栅极两侧的源/漏区。隔离件形成在栅极的每一侧上，形成间隔物以进行以从源极/漏极区域中的鳍片的部分去除第三层。硬掩模层的第二层从源极/漏极区域中的鳍片的部分去除，并且源极/漏极区域中的鳍片被合并。

5. 发明申请

WO2013063351A1 THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS 审中-公开
标题翻译：用于薄体MOSFET的阈值电压调整
公开(公告)号：WO2013063351A1
公开(公告)日：2013-05-02
申请号：PCT/US2012/062048
申请日：2012-10-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BRODSKY, Mary, Jane , CAI, Ming , GUO, Dechao , HENSON, William, K. , NARASIMHA, Shreesh , LIANG, Yue , SONG, Liyang , WANG, Yanfeng , YEH, Chun-chen
IPC分类号： H01L29/786
CPC分类号： H01L29/66803
摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
摘要翻译：一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。还公开了制造FinFET晶体管的方法。还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

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