专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2004049441A3 LOW THERMAL BUDGET FABRICATION OF FERROELECTRIC MEMORY USING RTP 审中-公开
标题翻译：使用RTP的电热记忆的低热预算制造
公开(公告)号：WO2004049441A3
公开(公告)日：2004-09-02
申请号：PCT/US0337501
申请日：2003-11-20
申请人： SYMETRIX CORP
发明人： CELINSKA JOLANTA , JOSHI VIKRAM , SOLAYAPPAN NARAYAN , LIM MYOUNGHO , MCMILLAN LARRY D , PAZ DE ARAUJO CARLOS A
IPC分类号： C30B29/32 , C30B29/68 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/115 , H01L29/78
CPC分类号： H01L28/55 , C30B29/32 , C30B29/68
摘要： A layered superlattice material precursor is applied to a substrate (102). The precursor coating is rapid thermal processed (RTP) with a ramping rate of 100 °C/second at a hold temperature in a range of from 500 °C to 900 °C for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell (100), the coating is heated in oxygen using RTP, then a top electrode layer (128) is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film (126) preferably has a thickness in a range of from 25 nm to 120 nm. The process typically has a thermal budget value not exceeding 960,000 °C-sec, preferably less than 50,000 °C-sec.
摘要翻译：将层状超晶格材料前体施加到基底（102）上。前体涂层是在500℃至900℃范围内的保持温度下以100℃/秒的升高速率进行快速热处理（RTP），累积加热时间不超过30分钟，优选小于 5分钟。在制造铁电存储单元（100）时，使用RTP在氧气中加热涂层，然后形成顶部电极层（128），然后使用RTP在氧气中或在非反应性气体中形成包含涂层的基板，形成顶部电极层。薄膜（126）优选具有在25nm至120nm范围内的厚度。该方法通常具有不超过960,000℃-sec，优选小于50,000℃-sec的热预算值。

2. 发明申请

WO02073669A3 METHOD OF MAKING LAYERED SUPERLATTICE MATERIAL WITH IMPROVED MICROSTRUCTURE 审中-公开
标题翻译：使用改进的微结构制备层状超导材料的方法
公开(公告)号：WO02073669A3
公开(公告)日：2003-03-20
申请号：PCT/US0145392
申请日：2001-10-30
申请人： SYMETRIX CORP , SEIKO EPSON CORP , KARASAWA JUNICHI , JOSHI VIKRAM
发明人： KARASAWA JUNICHI , JOSHI VIKRAM
IPC分类号： H01L27/105 , H01L21/02 , H01L21/311 , H01L21/314 , H01L21/316 , H01L21/8246
CPC分类号： H01L28/56 , H01L21/31122 , H01L21/31691
摘要： In the manufacture of an integrated circuit, a first electrode (48) is formed on a substrate (28). In a first embodiment, a strontium bismuth tantalate layer (50) and a second electrode (52) are formed on top of the first electrode (48). Prior to the final crystallization anneal, the first electrode (48), the strontium bismuth tantalate layer (50) and the second electrode (52) are patterned. The final crystallization anneal is then performed on the substrate (28). In a second embodiment, a second layer (132) of strontium bismuth tantalate is deposited on top of the strontium bismuth tantalate layer (50) prior to the forming of the second electrode (52) on top of the first and second layers (50), (132). In a third embodiment, a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50). In a fourth embodiment, an additional rapid thermal annealing process is performed on a substrate subsequent to the patterning process and prior to the final crystallization annealing process.
摘要翻译：在集成电路的制造中，在基板（28）上形成第一电极（48）。在第一实施例中，在第一电极（48）的顶部上形成钽酸铋铋层（50）和第二电极（52）。在最终结晶退火之前，对第一电极（48），钽酸锶锶层（50）和第二电极（52）进行图案化。然后在衬底（28）上进行最终的结晶退火。在第二实施例中，在第一和第二层（50）的顶部形成第二电极（52）之前，将钽酸铋锶的第二层（132）沉积在钽酸锶钽酸盐层（50）的顶部上，，（132）。在第三实施例中，对钽酸锶钽酸钡层（50）进行仔细控制的UV烘烤工艺。在第四实施例中，在图案化工艺之后并且在最终结晶退火工艺之前，对衬底进行附加的快速热退火工艺。

3. 发明申请

WO0169602A3 FERROELECTRIC MEMORY AND METHOD OF OPERATING SAME 审中-公开
标题翻译：电磁存储器及其操作方法
公开(公告)号：WO0169602A3
公开(公告)日：2002-02-21
申请号：PCT/US0105622
申请日：2001-02-22
申请人： SYMETRIX CORP
发明人： CHEN ZHENG , JOSHI VIKRAM , LIM MYOUNGHO , PAZ DE ARAUJO CARLOS A , MCMILLAN LARRY D
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric non-volatile memory (100, 436) comprising: a plurality of memory cells (14, 116, 117, 118, 119), each containing an FeFET (40, 140A) and a MOSFET (20, 120A), each of said FeFETs (14) having a source (42), a drain (44), a substrate (45), and a gate (58), and each MOSFET (20) having a pair of source/drains (22, 23) and a gate (21). The cells are arranged in an array comprising a plurality of rows (180) and a plurality of columns (184). A gate line (132) and a bit line (134) are associated with each column, and a word line (136), a drain line (139), and a substrate line (138) are associated with each row. A read MOSFET (160) is connected between a drain input (137) and the drain line associated with each row. The gate (165) of the read MOSFET is connected to an input for the read enable signal.
摘要翻译：一种铁电非易失性存储器（100,436），包括：多个存储单元（14,116,117,118,119），每个存储单元包含FeFET（40,140A）和MOSFET（20,120A），每个所述FeFET（14）具有源极（42），漏极（44），衬底（45）和栅极（58），并且每个MOSFET（20）具有一对源极/漏极（22,23）和一个门（21）。电池被布置成包括多个行（180）和多个列（184）的阵列。栅极线（132）和位线（134）与每列相关联，并且字线（136），漏极线（139）和衬底线（138）与每一行相关联。读取MOSFET（160）连接在漏极输入（137）和与每行相关联的漏极线之间。读取MOSFET的栅极（165）连接到用于读使能信号的输入端。

4. 发明申请

WO0175945A3 FERROELECTRIC INTEGRATED CIRCUIT HAVING HYDROGEN BARRIER LAYER 审中-公开
标题翻译：具有氢气阻隔层的电磁集成电路
公开(公告)号：WO0175945A3
公开(公告)日：2002-01-31
申请号：PCT/US0109892
申请日：2001-03-28
申请人： SYMETRIX CORP
发明人： CUCHIARO JOSEPH D , PAZ DE ARAUJO CARLOS A , MCMILLAN LARRY D
IPC分类号： H01L21/02 , H01L27/115 , H01L27/108 , H01L29/92
CPC分类号： H01L27/11502 , H01L28/55 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A hydrogen diffusion barrier (130, 330) in an integrated circuit (170, 270, 370, 470) is located to inhibit diffusion of hydrogen to a thin film (124) of metal oxide material in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following nitrides: aluminum titanium nitride (Al2Ti3N6), aluminum silicon nitride (Al2Si3N6), aluminum niobium nitride (AlNb3N6), aluminum tantalum nitride (AlTa3N6), aluminum copper nitride (Al2Cu3N4), tungsten nitride (WN), and copper nitride (Cu3N2). The thin film of metal oxide is ferroelectric or high-dielectric, nonferroelectric material. Preferably, the metal oxide comprises ferroelectric layered superlattice material. Preferably, the hydrogen barrier layer is located directly over the thin film of metal oxide.
摘要翻译：位于集成电路（170,270,370,470）中的氢扩散阻挡层（130,330）被设置成阻止氢扩散到集成电路中的金属氧化物材料的薄膜（124）。氢扩散阻挡层包括以下氮化物中的至少一种：氮化钛铝（Al 2 Ti 3 N 6），氮化硅铝（Al 2 Si 3 N 6），氮化铌（AlNb 3 N 6），氮化铝铝（AlTa 3 N 6），氮化铝铝（Al 2 Cu 3 N 4）（WN）和氮化铜（Cu3N2）。金属氧化物的薄膜是铁电或高电介质非电介质材料。优选地，金属氧化物包括铁电层状超晶格材料。优选地，氢阻挡层位于金属氧化物的薄膜的正上方。

5. 发明申请

WO0176771A2 LOW TEMPERATURE OXIDIZING METHOD OF MAKING A LAYERED SUPERLATTICE MATERIAL 审中-公开
标题翻译：制备层状超导材料的低温氧化方法
公开(公告)号：WO0176771A2
公开(公告)日：2001-10-18
申请号：PCT/US0109634
申请日：2001-03-22
申请人： SYMETRIX CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： JOSHI VIKRAM , CELINSKA JOLANTA , SOLAYAPPAN NARAYAN , MCMILLAN LARRY D , PAZ DE ARAUJO CARLOS A , ARITA KOJI
IPC分类号： C30B7/00 , H01L21/316 , H01L27/115 , B05D3/04 , B05D3/02 , C30B29/68 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/11502 , C30B7/00 , C30B7/005 , C30B29/68 , H01L21/31691
摘要： A thin film of precursor for forming a layered superlattice material (124, 226, 624) is applied (324, 424) to an integrated circuit substrate (122, 224, 500, 622), then a strong oxidizing agent is applied (328, 330, 426, 428) at low temperature in a range of from 100 DEG C to 300 DEG C to the precursor thin film, thereby forming a metal oxide thin film. The strong oxidizing agent may be liquid or gaseous. An example of a liquid strong oxidizing agent is hydrogen peroxide. An example of a gaseous strong oxidizing agent is ozone. The metal oxide thin film is crystallized by annealing (336, 338, 432, 434) at elevated temperature in a range of from 500 DEG C to 700 DEG C, preferably not exceeding 650 DEG C, for a time period in a range of from 30 minutes to two hours. Annealing is conducted in an oxygen-containing atmosphere, preferably including water vapor. Treatment (332, 430) by ultraviolet (UV) radiation may precede annealing. RTP in a range of from 500 DEG C to 700 DEG C may precede annealing.
摘要翻译：将用于形成层状超晶格材料（124,226,624）的前体薄膜（324,424）施加到集成电路衬底（122,224,500,622）上，然后施加强氧化剂（328， 330,426,428），在低温下在100℃〜300℃的范围内与前体薄膜形成金属氧化物薄膜。强氧化剂可以是液体或气体。液体强氧化剂的实例是过氧化氢。气态强氧化剂的实例是臭氧。金属氧化物薄膜通过退火（336,338,432,434）在500℃至700℃，优选不超过650℃的升高温度下结晶，时间范围为 30分钟到两个小时。退火在含氧气氛中进行，优选包括水蒸汽。通过紫外（UV）辐射处理（332,430）可以在退火之前进行。退火前可以在500〜700℃的范围内进行RTP。

6. 发明申请

WO2009140299A3 SELF-STABILIZING SENSOR CIRCUIT FOR RESISTIVE MEMORIES 审中-公开
标题翻译：用于电阻记忆体的自稳定传感器电路
公开(公告)号：WO2009140299A3
公开(公告)日：2010-01-28
申请号：PCT/US2009043661
申请日：2009-05-12
申请人： SYMETRIX CORP , CELINSKA JOLANTA , PAZ DE ARAUJO CARLOS A , MCWILLIAMS CHRISTOPHER RANDOLP
发明人： CELINSKA JOLANTA , PAZ DE ARAUJO CARLOS A , MCWILLIAMS CHRISTOPHER RANDOLPH
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2213/32
摘要： An integrated circuit resistance memory comprising: a memory cell comprising a variable resistance element capable of having a low resistance state and a high resistance state; a sensing circuit for sensing the resistance of the variable resistance element, the sensing circuit comprising a Wheatstone bridge circuit; and wherein the variable resistance element in the memory cell is electrically connectable to provide at least a portion of the resistance in one leg of the Wheatstone bridge circuit.
摘要翻译：一种集成电路电阻存储器，包括：存储单元，包括能够具有低电阻状态和高电阻状态的可变电阻元件; 感测电路，用于感测可变电阻元件的电阻，感测电路包括惠斯通电桥电路; 并且其中所述存储单元中的所述可变电阻元件可电连接以提供所述惠斯通电桥电路的一条支路中的至少一部分电阻。

7. 发明申请

WO0225667A2 FERROELECTRIC MEMORY AND METHOD OF OPERATING SAME 审中-公开
标题翻译：铁电存储器及其操作方法
公开(公告)号：WO0225667A2
公开(公告)日：2002-03-28
申请号：PCT/US0142288
申请日：2001-09-25
申请人： SYMETRIX CORP , MATSUSHITA ELECTRIC IND CO LTD , CHEN ZHENG , KATO YOSHIHISA , JOSHI VIKRAM , LIM MYOUNGHO , PAZ DE ARAUJO CARLOS A , MCMILLAN LARRY D , SHIMADA YASUHIRO , OTSUKI TATSUO
发明人： CHEN ZHENG , KATO YOSHIHISA , JOSHI VIKRAM , LIM MYOUNGHO , PAZ DE ARAUJO CARLOS A , MCMILLAN LARRY D , SHIMADA YASUHIRO , OTSUKI TATSUO
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.
摘要翻译：铁电存储器636包括一组存储单元（645,12,201,301,401,501），每个单元具有铁电存储元件（44,218等），驱动线（122,322,422等） 522等），在其上放置用于向该组存储器单元写入信息的电压;位线（25,49,125,325,425,525等），在该位线上将要从其中读出信息存储器单元被放置在存储器单元与位线之间的前置放大器（20,42,120,320,420等），连接在存储器单元与位线之间的置位开关（14,114,314,414,514等）驱动线和存储器单元，以及与前置放大器并联连接到存储器单元的复位开关（16,116,316,416,516等）。通过在存储元件上放置比铁电存储元件的矫顽电压小的电压来读取存储器。在读取之前，通过使铁电存储器元件的两个电极接地来放电来自电池组的噪声。

8. 发明申请

WO0077832A3 METAL OXIDE THIN FILMS FOR HIGH DIELECTRIC CONSTANT APPLICATIONS 审中-公开
标题翻译：用于高介电常数应用的金属氧化物薄膜
公开(公告)号：WO0077832A3
公开(公告)日：2001-09-07
申请号：PCT/US0015956
申请日：2000-06-09
申请人： SYMETRIX CORP , MATSUSHITA ELECTRONICS CORP
发明人： HAYASHI SHINICHIRO , JOSHI VIKRAM , SOLAYAPPAN NARAYAN , CUCHIARO JOSEPH D , PAZ DE ARAUJO CARLOS A
IPC分类号： C01G35/00 , G11C11/22 , H01L21/314 , H01L21/316 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/06 , H01L27/105 , H01L27/108 , H01L29/78 , H01L29/788 , H01L29/792 , H01L27/115
CPC分类号： G11C11/22 , G11C11/223 , H01L21/31691 , H01L27/0629 , H01L29/78391
摘要： A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulae AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1-x)(TayNb1-y)2O6,where 0 /=40, and preferably about 100. The value of Vcc in the metal oxides of the invention is close to zero. The value of Tcc is
摘要翻译：一种高介电常数绝缘体，包括选自钨青铜型氧化物，烧绿石型氧化物和Bi 2 O 3与选自钙钛矿和烧绿石型氧化物的氧化物的组合的金属氧化物的薄膜。一个实施方案包含由一般化学计量式AB2O6，A2B2O7和A2B2B2O10表示的金属氧化物，其中A表示选自由Ba，Bi，Sr，Pb，Ca，K，Na和La组成的金属组中的A位原子; B表示选自由Ti，Zr，Ta，Hf，Mo，W和Nb组成的金属组中的B位原子。优选地，金属氧化物是（BaxSr1-x）（TayNb1-y）2O6，其中0≤x≤1.0且0≤y≤1.0; （BaxSr1-x）2（TayNb1-y）2O7，其中0≤x≤1.0且0≤y≤1.0; 和（BaxSr1-x）2Bi2（TayNb1-y）2O10，其中0≤x≤1.0且0≤y≤1.0。根据本发明的薄膜的相对介电常数≥40，优选约为100.本发明金属氧化物中的Vcc值接近零。 Tcc的值<1000ppm，优选<100。

9. 发明申请

WO9734320A9 METHOD AND APPARATUS FOR FABRICATING SILICON DIOXIDE AND SILICON GLASS LAYERS IN INTEGRATED CIRCUITS 审中-公开
标题翻译：在一体化电路中制造二氧化硅和硅玻璃层的方法和装置
公开(公告)号：WO9734320A9
公开(公告)日：1999-12-16
申请号：PCT/US9704185
申请日：1997-03-14
申请人： SYMETRIX CORP , MATSUSHITA ELECTRONICS CORP
发明人： MCMILLAN LARRY D , SCOTT MICHAEL C , PAZ DE ARAUJO CARLOS A , OTSUKI TATSUO , HAYASHI SHINICHIRO
IPC分类号： B05D1/00 , B05D3/04 , B05D7/24 , C23C16/44 , C23C16/448 , C23C16/455 , C23C16/46 , C23C16/48 , C23C16/52 , C23C18/12 , C23C18/14 , C23C26/02 , C30B7/00 , H01L21/02 , H01L21/314 , H01L21/316 , H01L27/115 , H01L41/24 , H05K3/10
CPC分类号： H01L21/316 , B05D1/00 , B05D1/60 , B05D3/0493 , C23C16/4412 , C23C16/4486 , C23C16/45561 , C23C16/4558 , C23C16/46 , C23C16/482 , C23C16/52 , C23C18/1212 , C23C18/1287 , C23C18/14 , C23C26/02 , C30B7/00 , C30B29/68 , H01L21/314 , H01L21/31691 , H01L27/11502 , H01L28/55 , H01L28/56 , H01L28/60 , H01L41/316 , H05K3/105
摘要： A precursor liquid (64) comprising silicon in a xylene solvent is prepared, a substrate (5, 71) is placed within a vacuum deposition chamber (2), the precursor liquid is misted, and the mist (66) is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried, baked, and annealed to form a thin film (1224, 77) of silicon dioxide or silicon glass on the substrate. Then an integrated circuit (100) is completed to include at least a portion of the silicon dioxide or silicon glass layer as an insulator (77) for an electronic device (76) in the integrated circuit.
摘要翻译：制备在二甲苯溶剂中含硅的前体液体（64），在真空沉积室（2）内放置基材（5,71），使前体液体雾化，并将雾（66）流入沉积物同时将室保持在环境温度下，以将一层前体液体沉积在基底上。将液体干燥，烘烤和退火，以在基底上形成二氧化硅或硅玻璃的薄膜（1224,77）。然后完成集成电路（100），以将至少一部分二氧化硅或硅玻璃层作为用于集成电路中的电子器件（76）的绝缘体（77）。

10. 发明申请

WO2004066307A3 STACKED MEMORY CELL HAVING DIFFUSION BARRIERS 审中-公开
标题翻译：具有扩展障碍的堆叠存储单元
公开(公告)号：WO2004066307A3
公开(公告)日：2004-09-23
申请号：PCT/US2004001391
申请日：2004-01-20
申请人： SYMETRIX CORP
发明人： JOSHI VIKRAM , SOLAYAPPAN NARAYAN , PAZ DE ARAUJO CARLOS A , MCMILLAN LARRY D
IPC分类号： C30B29/32 , C30B29/68 , G11C20060101 , H01L21/02 , H01L21/314 , H01L21/8246 , H01L23/64 , H01L27/115
CPC分类号： H01L27/11502 , C30B29/32 , C30B29/68 , H01L23/642 , H01L27/11507 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A bottom electrode (238) and portion of an insulator layer (224) adjacent to the bottom electrode of a memory capacitor (540) are removed by etching to form sidewall (440) and a moat region (450) in the insulator. A nonconductive oxygen barrier layer (460) is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier (444, 236) beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch (208). A nonconductive hydrogen barrier layer (508), the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film (490) in the capacitor.
摘要翻译：通过蚀刻去除底部电极（238）和与存储电容器（540）的底部电极相邻的绝缘体层（224）的部分，以在绝缘体中形成侧壁（440）和护环区域（450）。沉积非导电氧阻挡层（460）以覆盖护城河的侧壁和底部。电容器下方的非导电氧阻挡层和导电扩散阻挡层（444,236）一起在电容器和开关（208）之间提供基本上连续的扩散阻挡层。不导电氢阻挡层（508），非导电氧阻挡层和导电扩散阻挡层基本上完全包围电容器，特别是电容器中的铁电薄膜（490）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式