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81. 发明申请

WO2016187443A1 TRANSACTIONAL COMMITS WITH HARDWARE ASSISTS IN REMOTE MEMORY 审中-公开
标题翻译：与远程存储器中的硬件辅助部件的交互式组件
公开(公告)号：WO2016187443A1
公开(公告)日：2016-11-24
申请号：PCT/US2016/033306
申请日：2016-05-19
申请人： PURE STORAGE, INC.
发明人： HAYES, John , GOLD, Brian , GUPTA, Shantanu , LEE, Robert , KANNAN, Hari
IPC分类号： G06F12/06 , G06F13/16 , G06F12/02 , G06F3/06
CPC分类号： G06F3/0688 , G06F3/0619 , G06F3/0656 , G06F9/467 , G06F13/16
摘要： A method for a transactional commit in a storage unit is provided. The method includes receiving a logical record from a storage node into a transaction engine of a storage unit of the storage node and writing the logical record into a data structure of the transaction engine. The method includes writing, to a command queue of the transaction engine, an indication to perform an atomic update using the logical record and transferring each portion of the logical record from the data structure of the transaction engine to non-persistent memory of the storage unit as a committed transaction. A storage unit for a storage system is also provided.
摘要翻译：提供了一种在存储单元中进行事务提交的方法。该方法包括从存储节点接收逻辑记录到存储节点的存储单元的事务引擎中，并将该逻辑记录写入到事务引擎的数据结构中。该方法包括向事务引擎的命令队列写入使用逻辑记录执行原子更新的指示，并将逻辑记录的每个部分从事务引擎的数据结构转移到存储单元的非持久存储器作为承诺交易。还提供了一种用于存储系统的存储单元。

82. 发明申请

WO2016105787A1 SYSTEMS, APPARATUSES, AND METHODS FOR DATA SPECULATION EXECUTION 审中-公开
标题翻译：用于数据规范执行的系统，设备和方法
公开(公告)号：WO2016105787A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062255
申请日：2015-11-24
申请人： INTEL CORPORATION
发明人： OULD-AHMED-VALL, Elmoustapha , HUGHES, Christopher J. , VALENTINE, Robert , GIRKAR, Milind B.
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3016 , G06F9/30043 , G06F9/30047 , G06F9/30065 , G06F9/30087 , G06F9/30098 , G06F9/34 , G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F9/467
摘要： Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode, and execution hardware to execute the decoded instruction to reset data speculative execution (DSX) tracking hardware to track speculative memory accesses, clear a DSX status indication in a DSX status register, and commit all speculatively executed stores of the DSX region and thereby end a DSX region.
摘要翻译：描述用于数据推测执行（DSX）的系统，方法和装置。在一些实施例中，用于执行DSX的硬件装置包括用于解码指令的硬件解码器，包括操作码的指令和执行硬件，以执行解码指令以复位数据推测执行（DSX）跟踪硬件以跟踪推测性存储器访问，在DSX状态寄存器中清除DSX状态指示，并提交DSX区域的所有推测执行的存储，从而结束一个DSX区域。

83. 发明申请

WO2016097681A1 MONITORING UTILIZATION OF TRANSACTIONAL PROCESSING RESOURCE 审中-公开
标题翻译：监测交易处理资源的利用
公开(公告)号：WO2016097681A1
公开(公告)日：2016-06-23
申请号：PCT/GB2015/053570
申请日：2015-11-24
申请人： ARM LIMITED
发明人： DIESTELHORST, Stephan , HORSNELL, Matthew James
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F9/467 , G06F9/3842 , G06F11/362
摘要： An apparatus (2) may have a processing element (4) for performing data access operations to access data from at least one storage device (10, 12, 14). The processing element may have at least one transactional processing resource (10, 18) supporting processing of a transaction in which data accesses are performed speculatively following a transaction start event and for which the speculative results are committed in response to a transaction end event. Monitoring circuitry (30) captures monitoring data indicating a degree of utilization of the transactional processing resource (10, 18) when processing the transaction.
摘要翻译：设备（2）可以具有用于执行数据访问操作以从至少一个存储设备（10,12,14）访问数据的处理元件（4）。处理元件可以具有至少一个支持事务处理的事务处理资源（10,18），其中数据访问在事务开始事件之后被推测地执行，并且响应于事务结束事件提供推测结果。当处理交易时，监视电路（30）捕获指示事务处理资源（10,18）的利用程度的监控数据。

84. 发明申请

WO2016092344A1 PATTERN DETECTOR FOR DETECTING HANGS 审中-公开
标题翻译：用于检测HANGS的图案检测器
公开(公告)号：WO2016092344A1
公开(公告)日：2016-06-16
申请号：PCT/IB2014/003149
申请日：2014-12-13
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： HOOKER, Rodney, E. , REED, Douglas, R.
IPC分类号： G06F12/00
CPC分类号： G06F12/0855 , G06F9/38 , G06F9/382 , G06F9/467 , G06F9/524 , G06F12/0877 , G06F12/0895 , G06F12/0897 , G06F2212/40
摘要： A microprocessor comprises a cache including a tag array; a tag pipeline that arbitrates access to the tag array; and a pattern detector. The pattern detector comprises a register; a decoder that decodes transaction type identifiers of tagpipe arbs advancing through the tag pipeline; and an accumulator that accumulates into the register the transaction type identifiers of a plurality of tagpipe arbs that advance through the tag pipeline.
摘要翻译：微处理器包括包括标签阵列的高速缓存器; 标记流水线，用于仲裁对标签数组的访问; 和图案检测器。模式检测器包括寄存器; 解码器，其解码通过标签管道前进的标记栏的交易类型标识符; 以及累加器，其向所述寄存器中累积通过所述标签流水线前进的多个标记栏的交易类型标识符。

85. 发明申请

WO2015198009A1 A DEVICE CONTROLLER AND METHOD FOR PERFORMING A PLURALITY OF WRITE TRANSACTIONS ATOMICALLY WITHIN A NONVOLATILE DATA STORAGE DEVICE 审中-公开
标题翻译：一种用于在非易失性数据存储设备中进行多重写入交易的设备控制器和方法
公开(公告)号：WO2015198009A1
公开(公告)日：2015-12-30
申请号：PCT/GB2015/051467
申请日：2015-05-19
申请人： ARM LIMITED
发明人： DE JONG, Irenéus Johannes , HANSSON, Andreas
IPC分类号： G06F12/02 , G06F3/06 , G06F13/16
CPC分类号： G06F3/061 , G06F3/06 , G06F3/0656 , G06F3/0679 , G06F9/467 , G06F12/0246 , G06F12/0253 , G06F12/0802 , G06F12/10 , G06F13/16 , G06F2212/222 , G06F2212/65 , G06F2212/7201
摘要： A device controller and method are provided for performing a plurality of write transactions atomically within a non-volatile data storage device. Each transaction specifies a logical address and the method comprises creating an address translation map for the logical addresses specified by the plurality of write transactions, by referencing an address translation record within the non-volatile data storage device to determine for each logical address a corresponding physical address within the data storage device. Further, if the corresponding physical address indicated in the address translation record already contains valid data, the logical address is remapped to a new physical address in the address translation map. However, at this point the address translation record as stored in the data storage device is not updated. Instead, the plurality of write transactions are performed using the logical address to physical address mapping in the address translation map. Then, only once the plurality of write transactions have been performed is the address translation record updated in the non- volatile data storage device in order to identify the logical address to physical address mapping in the address translation map. Since, at the time of performing the write transactions, any new data that updates data already stored in the data storage device is written into a different physical address location, and hence the previous version of the data is still stored on the data storage device, and given that the address translation record is not updated unless the plurality of write transactions are actually performed atomically, then this enables the state held on the data storage device to be rolled back to the state that existed prior to performing the plurality of write transactions, if any event prevents that plurality of write transactions being performed atomically.
摘要翻译：提供了用于在非易失性数据存储设备内原子地执行多个写入事务的设备控制器和方法。每个事务指定逻辑地址，并且该方法包括通过引用非易失性数据存储设备内的地址转换记录来为多个写入事务指定的逻辑地址创建地址转换映射，以确定每个逻辑地址相应的物理数据存储设备内的地址。此外，如果地址转换记录中指示的对应的物理地址已经包含有效数据，则将逻辑地址重新映射到地址转换映射中的新的物理地址。然而，此时存储在数据存储装置中的地址转换记录不被更新。相反，使用地址转换映射中的逻辑地址到物理地址映射来执行多个写入事务。然后，只有一次执行多次写入事务是在非易失性数据存储设备中更新的地址转换记录，以便识别地址转换映射中的物理地址映射的逻辑地址。由于在执行写入事务时，将已经存储在数据存储装置中的数据的任何新数据写入不同的物理地址位置，因此数据的先前版本仍然存储在数据存储装置上，并且假定地址转换记录不被更新，除非多个写入事务实际上是以原子方式执行的，则这使得保持在数据存储设备上的状态能够回滚到在执行多个写入事务之前存在的状态，如果任何事件阻止多个写事务以原子方式执行。

86. 发明申请

WO2015165077A1 SYSTEM AND METHOD FOR PROVIDING DISTRIBUTED TRANSACTION LOCK IN TRANSACTIONAL MIDDLEWARE MACHINE ENVIRONMENT 审中-公开
标题翻译：用于提供交易中间件机器环境中分布式交易锁的系统和方法
公开(公告)号：WO2015165077A1
公开(公告)日：2015-11-05
申请号：PCT/CN2014/076602
申请日：2014-04-30
申请人： ORACLE INTERNATIONAL CORPORATION , ZHENG, Yunrong
发明人： ZHENG, Yunrong , LITTLE, Todd J. , HEEREN, Edward A. , CAI, Jimin , LI, Xiangdong
IPC分类号： G06F12/14
CPC分类号： G06F9/467 , G06F9/46 , G06F17/30 , G06F17/3033 , G06F17/30362 , G06F17/30371
摘要： A system and method can support a distributed transaction lock in a transactional middleware machine environment. The system can use a global transaction identifier to locate a hash bucket in a transaction hash table, wherein the transaction hash table contains a plurality of hash buckets. Then, the system can lock said hash bucket in the transaction hash table, and allow only one process to access one or more global transaction entry structures in the transaction table before said hash bucket is unlocked, wherein said one or more global transaction entry structures are associated with the locked hash bucket in the transaction hash table.
摘要翻译：系统和方法可以支持事务性中间件机器环境中的分布式事务锁定。系统可以使用全局事务标识符来定位事务散列表中的哈希桶，其中事务散列表包含多个哈希桶。然后，系统可以将事务哈希表中的所述哈希桶锁定，并且在所述哈希桶被解锁之前，只允许一个进程访问事务表中的一个或多个全局事务条目结构，其中所述一个或多个全局事务输入结构是与事务哈希表中的锁定哈希桶相关联。

87. 发明申请

WO2015153656A1 ATOMIC WRITES FOR MULTIPLE-EXTENT OPERATIONS 审中-公开
标题翻译：用于多种操作的原子写入
公开(公告)号：WO2015153656A1
公开(公告)日：2015-10-08
申请号：PCT/US2015/023664
申请日：2015-03-31
申请人： AMAZON TECHNOLOGIES, INC.
发明人： STRAUSS, Jacob A. , FRIGO, Matteo , HAUGLAND, Alex , OIKARINEN, Matti Juhani , VINCENT, Pradeep , HENDRICKSON, Joshua Samuel
IPC分类号： G06F17/30
CPC分类号： G06F9/467 , G06F9/466
摘要： A node of a storage service is selected as a coordinator of a distributed transaction involving multiple page-level modifications. The coordinator identifies other nodes as members of a node chain collectively storing physical data pages at which proposed modifications are to be performed, including a decider node responsible for a decision to commit the transaction. The coordinator generates a transaction preparation message comprising a representation of an order of respective commit decisions associated with the proposed modifications, and transmits the message to a selected node of the chain for a sequential propagation along the chain. Each chain node performs a local commit analysis for its changes and stores a record of its intent to commit. If a decision to commit is reached at the decider, the proposed modifications are completed.
摘要翻译：选择存储服务的节点作为涉及多个页面级修改的分布式事务的协调器。协调器将其他节点标识为节点链的成员，共同存储将要执行所提出的修改的物理数据页，包括负责决定提交事务的决定节点。协调器生成交易准备消息，其包括与所提出的修改相关联的各自提交决定的顺序的表示，并且将消息发送到链的所选节点，以沿着链的顺序传播。每个链节点对其更改执行本地提交分析，并存储其提交意图的记录。如果决定者达成了作出决定，则建议的修改完成。

88. 发明申请

WO2015148679A1 METHOD AND PROCESSOR FOR PROCESSING DATA 审中-公开
标题翻译：用于处理数据的方法和处理器
公开(公告)号：WO2015148679A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/022507
申请日：2015-03-25
申请人： ALIBABA GROUP HOLDING LIMITED
发明人： MA, Ling , YAO, Sihai , ZHANG, Lei
IPC分类号： G06F15/16
CPC分类号： G06F12/0811 , G06F9/467 , G06F12/0808 , G06F2212/283
摘要： A multiprocessor system providing transactional memory. A first processor initiates a transaction which includes reading first data into a private cache of the first processor, and performing a write operation on the first data in the private cache of the first processor. In response to detecting that prior to the write operation the first data was last modified by a second processor, the first processor writes the modified first data into a last level cache (LLC) accessible by the multiple processors. The system sets a cache line state index string to indicate that the first data written into the LLC was last modified by the first processor, invalidates the first data in the private cache of the first processor, and commits the transaction to the transactional memory system. This allows more efficient accesses to the data by the multiple processors.
摘要翻译：提供事务性内存的多处理器系统。第一处理器启动事务，其包括将第一数据读入第一处理器的专用高速缓存，以及对第一处理器的专用高速缓存中的第一数据执行写入操作。响应于在写入操作之前检测到第一数据被第二处理器最后修改，第一处理器将修改的第一数据写入由多个处理器可访问的最后一级高速缓存（LLC）。系统设置高速缓存行状态索引字符串以指示写入LLC的第一数据最后被第一处理器修改，使第一处理器的专用高速缓存中的第一数据无效，并将事务提交给事务存储器系统。这允许由多个处理器更有效地访问数据。

89. 发明申请

WO2015128781A1 SALVAGING HARDWARE TRANSACTIONS 审中-公开
标题翻译： SALVAGING五金交易
公开(公告)号：WO2015128781A1
公开(公告)日：2015-09-03
申请号：PCT/IB2015/051264
申请日：2015-02-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM (CHINA) INVESTMENT COMPANY LIMITED
发明人： MICHAEL, Maged, Milad , GSCHWIND, Michael Karl , CAIN III, Harold, Wade , SALAPURA, Valentina , SCHWARZ, Eric, Mark
IPC分类号： G06F9/46
CPC分类号： G06F9/467 , G06F9/3004 , G06F9/30087 , G06F9/3838 , G06F9/466 , G06F11/0724 , G06F11/0778 , G06F11/14 , G06F11/1402 , G06F11/1407 , G06F11/141 , G06F11/1474 , G06F11/167 , G06F11/3409 , G06F12/00 , G06F12/0815 , G06F12/123
摘要： A transactional memory system salvages a partially executed hardware transaction. A processor of the transactional memory system determines information about an about-to-fail handler for transactional execution of a code region of a hardware transaction. The processor saves state information of the hardware transaction, the state information usable to determine whether the hardware transaction is to be salvaged or to be aborted. The processor detects an about-to-fail condition during the transactional execution of the hardware transaction. The processor, based on the detecting, executes the about-to-fail handler using the information about the about-to-fail handler, the about-to-fail handler determining whether the hardware transaction is to be salvaged or to be aborted．
摘要翻译：事务存储系统抢救部分执行的硬件事务。事务存储器系统的处理器确定关于硬件事务的代码区域的事务执行的关于到失败处理程序的信息。处理器保存硬件事务的状态信息，状态信息可用于确定硬件事务是要被抢救还是被中止。处理器在硬件事务的事务执行期间检测到即将到失败的情况。处理器基于检测，使用关于即将到失败处理程序的信息执行关于到失败的处理程序，即将到失败的处理器确定硬件事务是要被抢救还是被中止。

90. 发明申请

WO2015128755A1 DELAYING FLOATING INTERRUPTION WHILE IN TX MODE 审中-公开
标题翻译：在发送模式下延迟浮动中断
公开(公告)号：WO2015128755A1
公开(公告)日：2015-09-03
申请号：PCT/IB2015/050702
申请日：2015-01-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM JAPAN LIMITED
发明人： GREINER, Dan , SHUM, Chung-Lung, Kevin , GSCHWIND, Michael Karl , SALAPURA, Valentina
IPC分类号： G06F9/48
CPC分类号： G06F13/24 , G06F9/467
摘要： A computer implemented method and system for delaying a floating interruption while a processor is in a transactional-execution mode. A floating interruption mechanism can detect a floating interruption request for one or more floating interruption eligible processors. Based on each eligible processor being in TX mode, the method and system can delay, using a predetermined period of time, performing the floating interruption at a selected processor of the one or more of the processors. A first processor of the one or more processors can be selected based on the first processor exiting the transactional execution mode within the predetermined period of time. Based on the predetermined period of time expiring, the method and system can cause an interrupt to one of the plurality of processors, and the interrupt can cause the processor to abort a transaction.
摘要翻译：一种计算机实现的方法和系统，用于在处理器处于事务执行模式时延迟浮动中断。浮动中断机制可以检测一个或多个浮动中断合格处理器的浮动中断请求。基于每个符合条件的处理器处于TX模式，所述方法和系统可以使用预定时间段在所述处理器中的一个或多个处理器的选定处理器处执行浮动中断。可以基于在预定时间段内退出事务执行模式的第一处理器来选择一个或多个处理器的第一处理器。基于预定的时间段到期，该方法和系统可以对多个处理器中的一个处理器造成中断，并且中断可导致处理器中止事务。

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