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81. 发明申请

WO01031473A1 MULTIPLEXING N-DIMENSIONAL MESH CONNECTIONS ONTO (N + 1) DATA PATHS 审中-公开
标题翻译：（N + 1）数据块的多重N维连接
公开(公告)号：WO01031473A1
公开(公告)日：2001-05-03
申请号：PCT/US2000/041531
申请日：2000-10-25
IPC分类号： G06F15/173 , G06F15/80 , H04L29/06 , H04L29/08
CPC分类号： H04L67/1097 , G06F15/17337 , G06F15/17381 , G06F15/8023 , H04L29/06 , H04L69/329
摘要： A single-instruction multiple-data (SIMD) array processor (200) implemented using a plurality of Application Specific Integrated Circuits (ASIC's) that requires a smaller number of data I/O paths per ASIC for interconnection purposes. The SIMD array processor (200) includes an N-dimensional array of processor arrays (202, 204) in which each processor array includes an N-dimensional array of processing elements. Each processor array is implemented on a respective ASIC. Further, the 2N edges of each processor array are connected to (N + 1) data I/O paths (220a, 220b, 220c) that support communication with 2N dimensionally adjacent processor arrays implemented on respective ASIC's.
摘要翻译：使用多个专用集成电路（ASIC）实现的单指令多数据（SIMD）阵列处理器（200），其为了互连目的而需要每个ASIC较少数量的数据I / O路径。 SIMD阵列处理器（200）包括处理器阵列（202,204）的N维阵列，其中每个处理器阵列包括处理元件的N维阵列。每个处理器阵列在相应的ASIC上实现。此外，每个处理器阵列的2N个边缘连接到（N + 1）个数据I / O路径（220a，220b，220c），该数据I / O路径支持与在相应ASIC上实现的2N维度相邻的处理器阵列的通信。

82. 发明申请

WO0022545A2 DIGITAL PROCESSING DEVICE 审中-公开
标题翻译：数字处理设备
公开(公告)号：WO0022545A2
公开(公告)日：2000-04-20
申请号：PCT/NO9900308
申请日：1999-10-08
申请人： FAST SEARCH & TRANSFER ASA , HALAAS ARNE , SVINGEN BOERGE , LEISTAD GEIRR I
发明人： HALAAS ARNE , SVINGEN BOERGE , LEISTAD GEIRR I
IPC分类号： G06F7/24 , G06F15/173 , G06F15/80 , G06F15/76
CPC分类号： G06F15/17343 , G06F15/8023
摘要： A digital processing device P, generally configured as a regular tree with n+1 levels S0, S1, S2...Sn and degree k, is provided in the form of a circuit Pn on the level Sn and forms the root node of the tree, an underlying level Sn-q, q=1,2,...n-1, in the circuit P comprising generally k circuits Pn-q provided nested in the k circuits Pn-q+1 on the overlying level Sn-q+1, each circuit Pn-q+1 on this level comprising k circuits Pn-q. A for q=n defined zeroth level in the circuit Pn comprises from k +1 to k circuits P0 which form kernel processors in the processing device P and on the level S0 constitute the leaf nodes of the tree, the kernel processor P0 being provided nested in a number from 1 to k in each of the circuits P1 on the level S1. Each of the circuits P1, P2, ...Pn, comprises a logic unit E which generally is connected with circuits P0, P1,...Pn-1 provided nested in the former circuits on the nearest underlying level and is additionally adapted to connect nodes on the same or underlying levels in neighbour trees. Each of the circuits P0, P1,...Pn has additionally identical interfaces I, such that IP0=IP1=...IPn.
摘要翻译：通常被配置为具有n + 1级S0，S1，S2 ... Sn和度k的规则树的数字处理装置P以层次Sn上的电路Pn的形式提供，并且形成树，基本电平Sn-q，q = 1,2，... n-1，其包括嵌套在k 个电路Pn-q中的通常包括k个电路Pn-q 在叠加电平Sn-q + 1上+1，该电平上的每个电路Pn-q + 1包括k个电路Pn-q。对于电路Pn中的q = n定义的第零级的A包括从处理设备P中形成内核处理器的k +1到k

83. 发明申请

WO00022503A1 EFFICIENT COMPLEX MULTIPLICATION AND FAST FOURIER TRANSFORM (FFT) IMPLEMENTATION ON THE MANARRAY ARCHITECTURE 审中-公开
标题翻译： MANARRAY建筑的高效复用和快速傅立叶变换（FFT）实现
公开(公告)号：WO00022503A1
公开(公告)日：2000-04-20
申请号：PCT/US1999/023494
申请日：1999-10-08
IPC分类号： G06F9/38 , G06F9/30 , G06F15/16 , G06F15/173 , G06F15/80 , G06F17/14 , G06F17/16 , G06F7/50 , G06F7/52 , G06F17/10
CPC分类号： G06F15/82 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3853 , G06F9/3885 , G06F15/8023 , G06F15/8038 , G06F17/142
摘要： Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor (100) is employed along with specialized complex multiplication instructions and communication operations between the processing elements (101, 151, 153, 155) which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs (100) are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.
摘要翻译：提供了复数乘法结果和非常有效的快速傅里叶变换（FFT）的有效计算。并行阵列VLIW数字信号处理器（100）与处理元件（101,151,153,155）之间的专门的复数乘法指令和通信操作一起使用，这些操作与计算重叠以提供非常高的性能操作。使用紧密压缩的VLIW（100）的循环的连续迭代，允许有效地使用复数乘法管线硬件。此外，描述了用于支持组合乘法累加操作的有效技术。

84. 发明申请

WO99053413A1 PATTERN GENERATION AND SHIFT PLANE OPERATIONS FOR A MESH CONNECTED COMPUTER 审中-公开
标题翻译：用于网格连接计算机的图案生成和移动平面图操作
公开(公告)号：WO99053413A1
公开(公告)日：1999-10-21
申请号：PCT/US1999/007004
申请日：1999-04-09
IPC分类号： G06F15/80
CPC分类号： G06F15/8023
摘要： An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a mask register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming "supercells" within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register. These registers have bit values corresponding to respective columns (for the X Pattern register) and rows (for the Y Pattern register) of the array. Patterns can be propagated from these registers into corresponding rows and columns. Further these registers can be used to receive values representing the logical OR of signals generated by individual PEs within respective rows and columns. Further, a number of global data registers are used to store information which can be broadcast back into the processing array.
摘要翻译：用于处理数据的装置具有单指令多数据（SIMD）架构，以及提高性能和可编程性的许多特征。该装置包括处理元件的矩形阵列和控制器。该装置提供用于移动阵列内的图像数据的多种技术。第一种技术，ROLL选项，同时在阵列内沿相反方向移动图像平面。第二种技术，门控移位选项使得对于每个PE，对于每个PE的屏蔽寄存器中存储的值，对于每个PE，将图像平面正常移位到相邻的PE。第三种技术是进位传播选项，将来自多个PE的计算结合起来，以便通过在阵列内形成“超级单元”来在n个时钟内完成n位操作。该装置还包括多位X模式寄存器和多位Y模式寄存器。这些寄存器具有对应于阵列的相应列（X模式寄存器）和行（Y模式寄存器）的位值。模式可以从这些寄存器传播到相应的行和列。此外，这些寄存器可以用于接收表示由相应行和列中的各PE产生的信号的逻辑或的值。此外，使用多个全局数据寄存器来存储可以广播回到处理阵列中的信息。

85. 发明申请

WO1995026001A1 EFFICIENT DIRECT CELL REPLACEMENT FAULT TOLERANT ARCHITECTURE SUPPORTING COMPLETELY INTEGRATED SYSTEMS WITH MEANS FOR DIRECT COMMUNICATION WITH SYSTEM OPERATOR 审中-公开
标题翻译：有效的直接单元更换故障容错架构支持完整的集成系统，与系统操作员直接通信
公开(公告)号：WO1995026001A1
公开(公告)日：1995-09-28
申请号：PCT/CA1995000161
申请日：1995-03-22
申请人： NORMAN, Richard, S.
IPC分类号： G06F11/20
CPC分类号： G06F3/041 , G02F1/13318 , G02F1/135 , G06F3/043 , G06F11/20 , G06F11/2041 , G06F11/2051 , G06F15/8007 , G06F15/8023 , G09G3/20 , G09G3/2085 , G09G3/2088 , G09G2300/0809 , G09G2300/0842 , G09G2330/08 , G09G2330/10 , H01L27/148 , H01L27/14831
摘要： A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.
摘要翻译：一种数据处理系统，其包含具有足够冗余的单元的单元网络，其通过由备用单元直接逻辑地替换有缺陷的单元，以允许组织大的单片阵列，而无需组织不可校正的缺陷，其中单元具有多种有用的特性。根据本发明的数据处理系统克服了基于芯片的架构的芯片尺寸限制和片外连接瓶颈，单处理器架构的冯诺依曼瓶颈，并行处理架构的存储器和I / O瓶颈以及输入高分辨率显示器的带宽瓶颈，并支持将整个大规模并行数据处理系统集成到单个单一实体中。

86. 发明申请

WO1990004835A1 DIGITAL COMPUTER WITH MULTIPROCESSOR ARRANGEMENT 审中-公开
标题翻译：数字电脑与多用户安排
公开(公告)号：WO1990004835A1
公开(公告)日：1990-05-03
申请号：PCT/EP1989001162
申请日：1989-10-04
申请人： WENDT, Hans-Joachim
IPC分类号： G06F15/80
CPC分类号： G02F1/133621 , G06E1/00 , G06F15/8023 , H01L31/12
摘要： In a digital computer with multiprocessor arrangement, each processor is a highly integrated computer chip on a semiconductor basis connected to the other processors in the arrangement, which are of same design, via a highly meshed management system composed of meshes and nodes for transmitting digital signals. Peripheral devices such as keyboards, memories, monitors, image sensors, speech analysis units, speech synthesis units as well as transmitters are connected to the computer. According to the invention, the management system is a beam waveguide network. Each node (26) is associated with a processor (11) to which it is coupled via an optical emitter (21) and an optical receiver (22). The new types of chip interconnection which result and hence the high packing density of the chips and large number of cross-connections obtained are particularly advantageous. The computer network has a high functional density and the computer and peripherals are unaffected by electromagnetic influences.

87. 发明申请

WO1988007722A2 IMPROVEMENTS IN OR RELATING TO CELLULAR ARRAY PROCESSING DEVICES 审中-公开
标题翻译：改进或相关于细胞阵列加工设备
公开(公告)号：WO1988007722A2
公开(公告)日：1988-10-06
申请号：PCT/GB1988000235
申请日：1988-03-28
申请人： STONEFIELD SYSTEMS PLC , CONSIDINE, William, Howard
发明人： STONEFIELD SYSTEMS PLC
IPC分类号： G06F15/06
CPC分类号： G06T5/20 , G06F15/8023
摘要： In each processing element of an array an input gate arrangement IG is provided with parallel AND-gates, holding register and ranking network which can be selected to provide outputs (derived from multiple bit neighbouring pixel values) for supply to either a generally conventional processing element PE2 or to a processing circuit PES which together with element PE2 forms an enhanced processing element. A bit summing network (11) in the circuit PES forms a count value signal representing the number of bits of a predetermined logic type supplied to inputs of the network (11), e.g. from the parallel AND-gates in arrangement IG. This count value signal is processed in adder (12) and accumulator (13) for example to form a convolution image value. The ranking network in the arrangement IG can be used to select for further processing a neighbouring pixel value of predetermined rank. Thus the components provided in circuit PES supplement the generally conventional element PE2 to enable simultaneous processing of a plurality of corresponding bits (same bit plane) of neighbouring pixel values so that convolutions and other image processing operations previously requiring inordinate time or hardware outlay are made economically possible at high speed. The components provided in device PES can be used in providing addition, substraction, multiplication and division operations as well as geometric transformations at enhanced speed.
摘要翻译：在阵列的每个处理元件中，输入栅极布置IG具有并联的与门，保持寄存器和排序网络，其可被选择以提供输出（从多个位相邻像素值导出），以供应给通常的常规处理元件 PE2或与元件PE2一起形成增强处理元件的处理电路PES。电路PES中的位求和网络（11）形成表示提供给网络（11）的输入的预定逻辑类型的比特数的计数值信号，例如，来自布置IG中的并行AND门。该计数值信号在加法器（12）和累加器（13）中进行处理，以形成卷积图像值。布置IG中的排序网络可以用于选择用于进一步处理预定等级的相邻像素值。因此，电路PES中提供的组件补充了一般传统的元件PE2，以便能够同时处理相邻像素值的多个相应位（相同的位平面），以便经济地进行先前需要过度时间或硬件支出的卷积和其他图像处理操作可能在高速。设备PES中提供的组件可用于提供加法，减法，乘法和除法操作以及增强速度的几何变换。

88. 发明申请

WO1988001772A1 A SYSTEM TO ALLOCATE THE RESOURCES OF A VERY LARGE SCALE COMPUTER 审中-公开
标题翻译：一个分配非常大的计算机资源的系统
公开(公告)号：WO1988001772A1
公开(公告)日：1988-03-10
申请号：PCT/US1987002181
申请日：1987-08-28
申请人： THINKING MACHINES CORPORATION
发明人： THINKING MACHINES CORPORATION , HILLIS, W., Daniel
IPC分类号： G06F15/16
CPC分类号： G06F9/5066 , G06F9/3836 , G06F9/5077 , G06F11/165 , G06F11/1658 , G06F11/2041 , G06F11/2046 , G06F11/2094 , G06F12/0215 , G06F12/10 , G06F15/17343 , G06F15/17381 , G06F15/8023 , G06F15/803
摘要： A system for a massively parallel computer (330) allocates the computer's resources among a large number of users (310A-310N) in a time sharing environment. This is accomplished by dynamically dividing the computer (330) into independently usable processor arrays (400) that allows a multiplicity of data bases (470, 480, 490) to be run simultaneously. Further, each of the 1,000,000 possible physical processors (PPU) are able to simulate additional virtual processors on the order of 1,000,000,000,000. A device of this size can be shared by a large number of users (310A-310N) with each user operating on only a portion of the entire computer (330).
摘要翻译：用于大规模并行计算机（330）的系统在时间共享环境中在大量用户（310A-310N）之间分配计算机资源。这通过将计算机（330）动态地划分为允许多个数据库（470,480,490）同时运行来实现的独立可用的处理器阵列（400）来实现。此外，1,000,000个可能的物理处理器（PPU）中的每一个都能够模拟大约1,000,000,000,000的额外的虚拟处理器。这种尺寸的设备可以由大量用户（310A-310N）共享，每个用户仅在整个计算机（330）的一部分上操作。

89. 发明申请

WO2019046727A1 PROVIDING FLEXIBLE MATRIX PROCESSORS FOR PERFORMING NEURAL NETWORK CONVOLUTION IN MATRIX-PROCESSOR-BASED DEVICES 审中-公开
公开(公告)号：WO2019046727A1
公开(公告)日：2019-03-07
申请号：PCT/US2018/049105
申请日：2018-08-31
申请人： QUALCOMM INCORPORATED
发明人： VERRILLI, Colin, Beaton , HEDDES, Mattheus, Cornelis Antonius Adrianus , VAIDHYANATHAN, Natarajan , BHATTACHARYA, Koustav , DREYER, Robert
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/063 , G06F15/8023 , G06F17/16 , G06N3/04 , G06N3/0445 , G06N3/0454
摘要： Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devices is disclosed. In this regard, a matrix-processor-based device provides a central processing unit (CPU) and a matrix processor. The matrix processor reorganizes a plurality of weight matrices and a plurality of input matrices into swizzled weight matrices and swizzled input matrices, respectively, that have regular dimensions natively supported by the matrix processor. The matrix-processor-based device then performs a convolution operation using the matrix processor to perform matrix multiplication/accumulation operations for the regular dimensions of the weight matrices and the input matrices, and further uses the CPU to execute instructions for handling the irregular dimensions of the weight matrices and the input matrices (e.g., by executing a series of nested loops, as a non-limiting example). The matrix-processor-based device thus provides efficient hardware acceleration by taking advantage of dimensional regularity, while maintaining the flexibility to handle different variations of convolution.

90. 发明申请

WO2011077103A1 GEODESIC MASSIVELY-PARALLEL SUPERCOMPUTER 审中-公开
标题翻译：地质大理石平行超级计算机
公开(公告)号：WO2011077103A1
公开(公告)日：2011-06-30
申请号：PCT/GB2010/002338
申请日：2010-12-24
申请人： ARAS, Richard
发明人： ARAS, Richard
IPC分类号： G06F15/80 , G06F15/173 , G06F9/38
CPC分类号： G06F15/803 , G06F15/17375 , G06F15/8023
摘要： Communication latency, now a dominant factor in computer performance, makes physical size, density, and interconnect proximity crucial system design considerations. The present invention addresses consequential supercomputing hardware challenges: spatial packing, communication topology, and thermal management. A massively-parallel computer with dense, spherically framed, geodesic processor arrangement is described. As a mimic of the problem domain, it is particularly apt for climate modelling. However, the invention's methods scale well, are largely independent of processor technology, and apply to a wide range of computing tasks. The computer's interconnect features globally short, highly regular, and tightly matched distances. Communication modes supported include neighbour-to-neighbour messaging on a spherical-shell lattice, and a radial network for system-synchronous clocking, broadcast, packet-switched networking, and IO. A near-isothermal cooling system, physically divorcing heat source and sink, enables extraordinarily compact geodes with lower temperature operation, higher speed, and lower power consumption.
摘要翻译：通信延迟，现在是计算机性能的主要因素，使物理尺寸，密度和互连接近度至关重要的系统设计考虑。本发明解决了相应的超级计算硬件挑战：空间打包，通信拓扑和热管理。描述了具有密集，球形框架，测地线处理器布置的大型并行计算机。作为对问题领域的模拟，它特别适用于气候建模。然而，本发明的方法规模很大，在很大程度上独立于处理器技术，并且适用于广泛的计算任务。计算机的互连具有全球短，高度规则和紧密匹配的距离。支持的通信模式包括在球面外壳网格上的邻居消息传递，以及用于系统同步时钟，广播，分组交换网络和IO的径向网络。近等温冷却系统，物理离散的热源和水槽，使得能够具有更低温度操作，更高速度和更低功耗的特别紧凑的地线。

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