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61. 发明申请

WO9320507A3 CISC TO RISC INSTRUCTION TRANSLATION ALIGNMENT AND DECODING 审中-公开
标题翻译： CISC指令翻译对齐和解码
公开(公告)号：WO9320507A3
公开(公告)日：1994-01-06
申请号：PCT/JP9300417
申请日：1993-03-30
申请人： SEIKO EPSON CORP
发明人： COON BRETT , MIYAYAMA YOSHIYUKI , NGUYEN LE TRONG , WANG JOHANNES
IPC分类号： C10G1/00 , C10G17/02 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/76
CPC分类号： G06F9/30101 , C10G1/00 , C10G17/02 , G06F9/30145 , G06F9/30149 , G06F9/30152 , G06F9/30163 , G06F9/30167 , G06F9/3017 , G06F9/30174 , G06F9/30185 , G06F9/3816 , G06F9/382 , G06F9/3853
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instruction bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
摘要翻译：一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。下一个指令检测器基于所述指令字节集来确定第一指令的结束。提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。然后对复杂指令流中的剩余指令字节重复该过程。孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

62. 发明申请

WO2022087810A1 APPARATUS AND METHOD FOR MATRIX MULTIPLICATION USING PROCESSING-IN-MEMORY 审中-公开
公开(公告)号：WO2022087810A1
公开(公告)日：2022-05-05
申请号：PCT/CN2020/123867
申请日：2020-10-27
申请人： NEONEXUS PTE. LTD. , ZHENG, Qilin
发明人： ZHENG, Qilin
IPC分类号： G06F17/16 , G06F15/76 , G06F7/00
摘要： Embodiments of apparatus and method for matrix multiplication using processing-in-memory (PIM) are disclosed. In an example, an apparatus for matrix multiplication includes an array of tiles that each include one or more PIM blocks. A PIM block may include a hybrid-mode PIM block that may be configured into a digital mode or an analog mode. The PIM block configured into digital mode may perform operations associated with depth-wise (DW) convolution. On the other hand, a PIM block configured into analog mode may perform operations associated with point-wise (PW) convolution. A controller may be used to configure the PIM block into either digital mode or analog mode, depending on the computations.

63. 发明申请

WO2021162690A1 COMPONENT ACCESS TO ROM-STORED FIRMWARE CODE OVER FIRMWARE CONTROLLER-EXPOSED VIRTUAL ROM LINK 审中-公开
公开(公告)号：WO2021162690A1
公开(公告)日：2021-08-19
申请号：PCT/US2020/017903
申请日：2020-02-12
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： DOWER, Glen Douglas , SEILER, Peter
IPC分类号： G06F13/00 , G06F15/76
摘要： A read-only memory (ROM) stores firmware code for a hardware component. A firmware controller is directly physically connected to the hardware component and to the ROM. The firmware controller exposes a virtual ROM link to the hardware component. The hardware component accesses the firmware code over the virtual ROM link exposed by the firmware controller.

64. 发明申请

WO2020160653A1 METHOD AND SYSTEM FOR CONVOLUTION MODEL HARDWARE ACCELERATOR 审中-公开
公开(公告)号：WO2020160653A1
公开(公告)日：2020-08-13
申请号：PCT/CA2020/050136
申请日：2020-02-04
申请人： ZHANG, Lei , QIAN, Jun
发明人： ZHANG, Lei , QIAN, Jun
IPC分类号： G06F15/76 , G06F17/10 , G06N20/00
摘要： A method and system for a convolution model hardware accelerator. The method comprises receiving a stream of an input feature map into the one or more processors utilizing a convolution model that includes a plurality of convolution layers, for a given convolution layer within the plurality of convolution layers, reconfiguring a computational order for a plurality of hardware accelerator sub-blocks by re-shuffling a plurality of output filters among the plurality of sub-blocks, and in accordance with the reconfigured computational order, generating output features that are interpretive of the input feature map.

65. 发明申请

WO2019246064A1 CONFIGURABLE IN-MEMORY COMPUTING ENGINE, PLATFORM, BIT CELLS AND LAYOUTS THEREFORE 审中-公开
公开(公告)号：WO2019246064A1
公开(公告)日：2019-12-26
申请号：PCT/US2019/037686
申请日：2019-06-18
申请人： THE TRUSTEES OF PRINCETON UNIVERSITY
发明人： VERMA, Naveen , VALAVI, Hossein , JAI, Hongyang
IPC分类号： G06F9/02 , G06F11/28 , G06F12/08 , G06F15/16 , G06F15/76
摘要： Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations. An in-memory computing architecture, comprising: a reshaping buffer, configured to reshape a sequence of received data words to form massively parallel bit-wise input signals; plurality of CIM channel output signals to provide thereby a sequence of multi-bit output words; to provide thereby a sequence of multi-bit output words; control circuitry configured to cause the CIM array to perform a multi-bit computing operation on the input and accumulation signals using singlebit internal circuits and signals; and a near-memory computing path configured to provide the sequence of multi-bit output words as a computing result.

66. 发明申请

WO2019152772A1 SYSTEMS AND METHODS FOR POLICY EXECUTION PROCESSING 审中-公开
公开(公告)号：WO2019152772A1
公开(公告)日：2019-08-08
申请号：PCT/US2019/016242
申请日：2019-02-01
申请人： THE CHARLES STARK DRAPER LABORATORY, INC. , BOLING, Eli , DEHON, André , SUTHERLAND, Andrew, Barclay
发明人： BOLING, Eli , DEHON, André , SUTHERLAND, Andrew, Barclay , MILBURN, Steve, Eugene , SULLIVAN, Gregory, Timothy
IPC分类号： G06F21/52 , G06F12/0875 , G06F12/14 , G06F15/76 , G06F9/30 , G06F9/38 , G06F21/62 , G06F21/71
摘要： A system and method of processing instructions may comprise an application processing domain (APD) and a metadata processing domain (MTD). The APD may comprise an application processor executing instructions and providing related information to the MTD. The MTD may comprise a tag processing unit (TPU) having a cache of policy-based rules enforced by the MTD. The TPU may determine, based on policies being enforced and metadata tags and operands associated with the instructions, that the instructions are allowed to execute (i.e., are valid). The TPU may write, if the instructions are valid, the metadata tags to a queue. The queue may (i) receive operation output information from the application processing domain, (ii) receive, from the TPU, the metadata tags, (iii) output, responsive to receiving the metadata tags, resulting information indicative of the operation output information and the metadata tags; and (iv) permit the resulting information to be written to memory.

67. 发明申请

WO2018169911A1 RECONFIGURABLE PARALLEL PROCESSING 审中-公开
公开(公告)号：WO2018169911A1
公开(公告)日：2018-09-20
申请号：PCT/US2018/022106
申请日：2018-03-13
申请人： LI, Yuan , ZHU, Jianbin
发明人： LI, Yuan , ZHU, Jianbin
IPC分类号： G06F15/00 , G06F15/76
摘要： Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.

68. 发明申请

WO2018127278A1 ASYMMETRISCHE SYSTEM- UND NETZWERKARCHITEKTUR 审中-公开
公开(公告)号：WO2018127278A1
公开(公告)日：2018-07-12
申请号：PCT/EP2017/050130
申请日：2017-01-04
申请人： SCHWARTZ, Gerhard
发明人： SCHWARTZ, Gerhard
IPC分类号： G06F21/71 , H04L29/06 , H04L12/24 , G06F11/36 , G06F15/76
摘要： Die Erfindung bezieht sich auf eine neuartige System- und Netzwerkarchitektur, welche die Endbenutzer durch reduzierte Komplexität der von ihnen genutzten Infrastruktur entlastet. Durch den Wegfall von Prozessoren, Betriebssystemen und traditioneller Software auf der Anwenderseite wird die Nutzung der IT vereinfacht und das Einschleusen von Schadsoftware in die Geräte der Endbenutzer verhindert. Darüber hinaus ermöglicht die neue Architektur den Aufbau sicherer und effizienterer Netzwerke auch in Bezug auf loT und Industrie 4.0 sowie neue Geschäftsmodelle, und unterstützt sowohl Koexistenz als auch die Migration von der herkömmlichen Technik auf die neue Architektur.

69. 发明申请

WO2017010941A1 COMPUTER AUTOMATED SYSTEM AND METHOD 审中-公开
标题翻译：计算机自动化系统与方法
公开(公告)号：WO2017010941A1
公开(公告)日：2017-01-19
申请号：PCT/SG2016/050324
申请日：2016-07-11
申请人： THINXTREAM TECHNOLOGIES PTE. LTD.
发明人： SHET, Sanjiv Shrikant , RAJ, Ranga , LOW, Teck Lee
IPC分类号： G06F17/00 , G06F15/76
CPC分类号： G06F17/30569 , G06F17/30557 , G06F17/30572 , G06F17/30595 , G06N99/005 , G06Q10/00 , G06Q30/06
摘要： Embodiments disclosed include a platform for collecting, normalizing, aggregating, and presenting/processing data over a wide range of devices, machines and applications in real-time, in a wired or wireless networked framework. An embodiment includes a computer automated system and method for aggregating data from a plurality of devices and applications. Embodiments disclosed further include a system and method for normalizing data from a plurality of devices and applications, for canonical-izing all normalized and aggregated data, and via a graphical user interface, combining the aggregated and normalized data, and displaying the combined data in a display compatible format. The computer system is further configured to abstract a plurality of classes of devices via a data modeling language comprised in the configuration of the computer system.
摘要翻译：公开的实施例包括用于在有线或无线网络框架中实时地，在各种各样的设备，机器和应用上收集，规范化，聚集和呈现/处理数据的平台。一个实施例包括用于聚合来自多个设备和应用的数据的计算机自动化系统和方法。所公开的实施例还包括用于对来自多个设备和应用的数据进行归一化的系统和方法，用于规范化所有归一化和聚合的数据，以及经由图形用户界面组合聚合和归一化数据，并将组合数据显示在显示兼容格式。计算机系统还被配置为经由包括在计算机系统的配置中的数据建模语言来抽象多个类别的设备。

70. 发明申请

WO2016135712A1 HARDWARE INSTRUCTION GENERATION UNIT FOR SPECIALIZED PROCESSORS 审中-公开
标题翻译：专用处理器的硬件指令生成单元
公开(公告)号：WO2016135712A1
公开(公告)日：2016-09-01
申请号：PCT/IB2016/052248
申请日：2016-04-20
申请人： MIREPLICA TECHNOLOGY, LLC
发明人： JOHNSON, William
IPC分类号： G06F9/30 , G06F9/38 , G06F9/455 , G06T1/20 , G06F15/76
CPC分类号： G06F9/3016 , G06F9/3017 , G06F9/3881 , G06F9/3893 , G06F9/4552 , G06F15/76 , G06F15/80 , G06T1/20
摘要： Methods, devices and systems are disclosed that interface a host computer to a specialized processor. In an embodiment, an instruction generation unit comprises attribute, decode, and instruction buffer stages. The attribute stage is configured to receive a host- program operation code and a virtual host-program operand from the host computer and to expand the virtual host-program operand into an operand descriptor. The decode stage is configured to receive the first operand descriptor and the host-program operation code, convert the host-program operation code to one or more decoded instructions for execution by the specialized processor, and allocate storage locations for use by the specialized processor. The instruction buffer stage is configured to receive the decoded instruction, place the one or more decoded instructions into one or more instruction queues, and issue decoded instructions from at least one of the one or more instruction queues for execution by the specialized processor.
摘要翻译：公开了将主计算机与专用处理器连接的方法，装置和系统。在一个实施例中，指令生成单元包括属性，解码和指令缓冲级。属性级配置为从主机接收主机程序操作码和虚拟主机程序操作数，并将虚拟主机程序操作数扩展为操作数描述符。解码级被配置为接收第一操作数描述符和主机程序操作代码，将主机程序操作代码转换为一个或多个解码指令以供专门处理器执行，并分配专用处理器使用的存储位置。指令缓冲器级被配置为接收解码的指令，将一个或多个解码的指令放入一个或多个指令队列中，并从一个或多个指令队列中的至少一个指令队列发出解码的指令，以供专门的处理器执行。

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