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61. 发明申请

WO2008042129A2 LIQUID IMMERSION COOLED MULTICHIP MODULE 审中-公开
标题翻译：液体浸渍冷却多芯片模块
公开(公告)号：WO2008042129A2
公开(公告)日：2008-04-10
申请号：PCT/US2007020515
申请日：2007-09-20
申请人： TERADYNE INC , CEPEDA-RIZO JUAN , ESMAILPOUR MOHSEN , TENEKETGES NICHOLAS
发明人： CEPEDA-RIZO JUAN , ESMAILPOUR MOHSEN , TENEKETGES NICHOLAS
IPC分类号： H05K7/20 , H01L23/473
CPC分类号： G06F1/20 , G06F2200/201 , H01L23/44 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a liquid immersion cooled multichip module is provided which includes a substrate having chips mounted thereon and which is adapted to mount with a printed circuit board. A lid is adapted to secure to the printed circuit board so as to mount with the substrate to form a fluid chamber between the lid and the substrate, and to cause the substrate to mate with the printed circuit board. In one embodiment, a cambered bolster plate is located on a side of the printed circuit board opposite the lid and the lid is fastened to the bolster plate to secure the lid to the printed circuit board. A baffle, which may be removable in some embodiments, is located within the lid and directs coolant flow through the fluid chamber.
摘要翻译：在一个实施例中，提供了一种液浸冷却的多芯片模块，其包括其上安装有芯片并适于与印刷电路板安装的基板。盖适于固定到印刷电路板，以便与基板一起安装以在盖和基板之间形成流体室，并使基板与印刷电路板配合。在一个实施例中，弧形垫板位于印刷电路板的与盖子相对的一侧上，并且盖子固定到垫板上以将盖子固定到印刷电路板。在一些实施例中可以是可移除的挡板位于盖内并引导冷却剂流动通过流体室。

62. 发明申请

WO2008042114A2 SINE WAVE GENERATOR WITH DUAL PORT LOOK-UP TABLE 审中-公开
标题翻译：正弦波发生器与双端口查找表
公开(公告)号：WO2008042114A2
公开(公告)日：2008-04-10
申请号：PCT/US2007020318
申请日：2007-09-19
申请人： TERADYNE INC , GROSS DAVID MICHAEL , MCDONALD WILLIAM SCOTT
发明人： GROSS DAVID MICHAEL , MCDONALD WILLIAM SCOTT
CPC分类号： G06F1/0328 , G06F1/0353 , G06F1/0356
摘要： An automatic test system that includes low cost and accurate circuitry for generating sinusoidal signals. Each sinusoidal signal generator includes a look-up table that can, for each phase on sine wave, output two digital values representing an in-phase and a quadrature-phase value of the sine wave. Simple circuitry can be used to address the look-up table to output in-phase and quadrature-phase values. The in-phase and quadrature- phase values can be applied to down-stream circuitry, such as error correction circuitry, that uses an in-phase and a quadrature-phase value to process the sine wave without the need for a relatively complex phase shifter in the down-stream circuitry. A dual-port memory may be used to implement the look-up table so that both an in-phase and a quadrature-phase value may be obtained from a single block of memory that stores a representation of a sine wave.
摘要翻译：自动测试系统，包括低成本和精确的电路，用于生成正弦信号。每个正弦信号发生器包括一个查找表，该表可以针对正弦波上的每个相位输出表示正弦波的同相和正交相位值的两个数字值。可以使用简单的电路来寻址查找表以输出同相和正交相位值。同相和正交相位值可以应用于下游电路，例如纠错电路，它使用同相和正交相位值来处理正弦波，而不需要相对复杂的移相器在下游电路中。可以使用双端口存储器来实现查找表，使得可以从存储正弦波的表示的单个存储器块获得同相和正交相位值。

63. 发明申请

WO2007053414A3 METHOD AND APPARATUS FOR ADJUSTMENT OF SYNCHRONOUS CLOCK SIGNALS 审中-公开
标题翻译：用于调整同步时钟信号的方法和装置
公开(公告)号：WO2007053414A3
公开(公告)日：2007-09-13
申请号：PCT/US2006041744
申请日：2006-10-26
申请人： TERADYNE INC , CONNER GEORGE W
发明人： CONNER GEORGE W
IPC分类号： H04L7/033
CPC分类号： H04L7/033 , H04L7/0008 , H04L7/0037 , H04L7/0337
摘要： A synchronous clock signal can be adjusted relative to a data signal by decreasing a delay in the synchronous clock signal if a transition of a data signal occurs before a pulse of an offset clock signal which is delayed by one half cycle relative to the synchronous clock signal. The synchronous clock signal can be delayed if the transition of the data signal occurs after the pulse of the offset synchronous clock signal.
摘要翻译：如果在相对于同步时钟信号延迟了半个周期的偏移时钟信号的脉冲之前发生数据信号的转变，则可以通过减少同步时钟信号的延迟来相对于数据信号来调整同步时钟信号。如果数据信号的转变发生在偏移同步时钟信号的脉冲之后，则可以延迟同步时钟信号。

64. 发明申请

WO2007081421A1 AUTOMATIC TESTING EQUIPMENT INSTRUMENT CARD AND PROBE CABLING SYSTEM AND APPARATUS 审中-公开
标题翻译：自动测试设备仪器卡和探测系统和设备
公开(公告)号：WO2007081421A1
公开(公告)日：2007-07-19
申请号：PCT/US2006/041964
申请日：2006-10-27
申请人： TERADYNE, INC. , PARRISH, Frank, B. , BEHZIZ, Arash
发明人： PARRISH, Frank, B. , BEHZIZ, Arash
IPC分类号： G01R31/28 , G01R1/073
CPC分类号： G01R31/2889 , G01R1/07378
摘要： A device for interfacing a test head and a prober is disclosed using wires or cables to provide the connection from a probe card interface boards to the probe card. The use of wires or cables, in place of the traditional pogo pin arrangement allows for more reliable and efficient testing, as well as additional high performance tests to be run. Optionally, a probe interface contains a stiffening member with multiple sidewalks and individual, configuration-specific probe card interface strips are connected to a probe card through zero insertion force clamps. The probe card interface attaches to the test head using standard probe interface board ("PIB") docking mechanics. The assembly is then connected to a probe to carry out the testing procedures.
摘要翻译：使用电线或电缆公开了用于连接测试头和探测器的装置，以提供从探针卡接口板到探针卡的连接。使用电线或电缆代替传统的pogo引脚布置，可以进行更可靠和高效的测试，以及进行额外的高性能测试。可选地，探针接口包含具有多个人行道的加强构件，并且单独的配置专用探针卡接口条通过零插入力夹具连接到探针卡。探头卡接口使用标准探头接口板（“PIB”）对接机构连接到测试头。然后将组件连接到探头以执行测试程序。

65. 发明申请

WO2007064604A1 ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：模拟数字转换器
公开(公告)号：WO2007064604A1
公开(公告)日：2007-06-07
申请号：PCT/US2006/045450
申请日：2006-11-28
申请人： TERADYNE, INC. , XU, Fang
发明人： XU, Fang
IPC分类号： H03M1/10
CPC分类号： H03M1/1042 , H03M1/167
摘要： Systems and techniques for converting an analog input value to an output digital code are described. A system includes a first internal analog-to-digital converter (ADC) configured to receive the analog input value and to convert it to a first digital code; a first internal digital-to-analog converter (DAC) configured to convert the first digital code to a first analog value; a first linearization module configured to receive the first digital code and to produce a first linear-correction code that is approximately equal to the first analog value; a second internal ADC configured to convert a remainder portion of the analog input value to a second digital code; and an accumulator configured to combine the first linear-correction code and the second digital code to produce the output digital code.
摘要翻译：描述用于将模拟输入值转换为输出数字代码的系统和技术。系统包括被配置为接收模拟输入值并将其转换为第一数字代码的第一内部模数转换器（ADC）第一内部数模转换器（DAC），被配置为将所述第一数字代码转换为第一模拟值; 第一线性化模块，被配置为接收所述第一数字码并产生近似等于所述第一模拟值的第一线性校正码; 第二内部ADC，被配置为将所述模拟输入值的剩余部分转换为第二数字代码; 以及累加器，被配置为组合第一线性校正码和第二数字码以产生输出数字码。

66. 发明申请

WO2007038480A1 PIN ELECTRONICS DRIVER 审中-公开
标题翻译： PIN电子驱动器
公开(公告)号：WO2007038480A1
公开(公告)日：2007-04-05
申请号：PCT/US2006/037413
申请日：2006-09-26
申请人： TERADYNE, INC. , SARTSCHEV, Ronald, A.
发明人： SARTSCHEV, Ronald, A.
IPC分类号： G01R31/319
CPC分类号： G01R31/31924
摘要： Circuitry for driving a pin of a device includes a first circuit path terminating in a first impedance, a second circuit path terminating in a second impedance, where the second impedance is less than the first impedance, and a selection circuit to control operation of the second circuit path. When the second circuit path is not configured for operation, the first circuit path is configured to output one of plural first voltage signals. When the second circuit path is in configured for operation, the second circuit path is configured to output a second voltage signal. The second voltage signal is greater than the plural first voltage signals.
摘要翻译：用于驱动装置的引脚的电路包括终止于第一阻抗的第一电路路径，终止于第二阻抗的第二电路路径，其中第二阻抗小于第一阻抗，以及选择电路，用于控制第二阻抗的操作电路路径。当第二电路不配置用于操作时，第一电路路径被配置为输出多个第一电压信号中的一个。当第二电路路径被配置用于操作时，第二电路路径被配置为输出第二电压信号。第二电压信号大于多个第一电压信号。

67. 发明申请

WO2007038340A2 STROBE TECHNIQUE FOR TIME STAMPING A DIGITAL SIGNAL 审中-公开
标题翻译：时间标记数字信号的频闪技术
公开(公告)号：WO2007038340A2
公开(公告)日：2007-04-05
申请号：PCT/US2006/037100
申请日：2006-09-22
申请人： TERADYNE, INC. , SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
发明人： SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
IPC分类号： H04B17/00
CPC分类号： G01R31/31937 , G01R31/31726 , G11C29/56 , G11C29/56004 , G11C29/56012
摘要： A system and apparatus generates a time-stamp to identify and record the time of an event such as an edge received in a data signal or clock signal. A set of strobe pulses can be generated by routing an external clock signal to delay elements with incrementally increasing delay values. A data signal or device under test clock signal can be applied to the input to each of a set of latches which are clocked by the strobe pulses. The set of latches can thereby capture a series of samples of the data signal or clock signal. The series of samples can be encoded as an edge time within a clock cycle. A clock cycle counter can be added to the edge time to generate the time stamp.
摘要翻译：系统和设备生成时间戳以识别和记录诸如在数据信号或时钟信号中接收的边缘的事件的时间。一组选通脉冲可以通过将外部时钟信号路由到延迟增加的延迟值的延迟元件来产生。数据信号或被测设备时钟信号可以被施加到由选通脉冲计时的一组锁存器中的每一个的输入。该组锁存器由此可以捕获数据信号或时钟信号的一系列样本。一系列采样可以被编码为一个时钟周期内的边沿时间。时钟周期计数器可以添加到边缘时间以生成时间戳。

68. 发明申请

WO2007005484A2 DEVICE AND METHOD TO REDUCE SIMULTANEOUS SWITCHING NOISE 审中-公开
标题翻译：减少同时切换噪声的装置和方法
公开(公告)号：WO2007005484A2
公开(公告)日：2007-01-11
申请号：PCT/US2006025245
申请日：2006-06-28
申请人： TERADYNE INC , MESSIER JASON
发明人： MESSIER JASON
IPC分类号： G01D3/00 , G06F12/00 , G06F17/50
CPC分类号： G06F17/5045
摘要： By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect.
摘要翻译：通过减少在转换期间改变值的驱动器的累积数量，可以减少累积电流变化以及同时的开关噪声效应。此外，减小的累积电流变化还可以减小芯片的接地和/或电源平面中的电压波动，从而最小化由于电压骤降或峰值引起的潜在的不正确的逻辑功能。在一个实现中，该方法包括读取第一字的第一组位的第一状态的值并获得第一组位中的每一个的第二状态的投影值。如果可以通过改变第一组位的第二状态的投影值来减小第一开关噪声累积效应，则确定具有与第二状态的投影值不同的至少一个值的一组替代值，以减少首先开关噪声累积效应。

69. 发明申请

WO2007005109A2 JITTER COMPENSATION AND GENERATION IN TESTING COMMUNICATION DEVICES 审中-公开
标题翻译：测试通信设备中的抖动补偿和生成
公开(公告)号：WO2007005109A2
公开(公告)日：2007-01-11
申请号：PCT/US2006017873
申请日：2006-05-09
申请人： TERADYNE INC , XU FANG
发明人： XU FANG
IPC分类号： H03K7/06 , H03D1/04
CPC分类号： H04L43/50
摘要： Methods, system, and computer programs for compensating for jitter in a communication system are described. A transfer function of a transmission medium is measured and an output signal that results from propagating an input signal through the transmission medium is calculated. Data dependent jitter is determined in the output signal. In memory, compensated edge positions of the input signal are stored. The compensated edge positions are arranged such that the data dependent jitter causes edge positions of the output signal to move closer to ideal edge positions.
摘要翻译：描述用于补偿通信系统中的抖动的方法，系统和计算机程序。测量传输介质的传递函数，并计算通过传输介质传播输入信号所产生的输出信号。数据相关抖动在输出信号中确定。在存储器中，存储输入信号的补偿边缘位置。补偿边缘位置被布置成使得数据相关的抖动导致输出信号的边缘位置移动到理想的边缘位置。

70. 发明申请

WO2006002355A3 COMPARATOR FEEDBACK PEAK DETECTOR 审中-公开
标题翻译：比较器反馈峰值检测器
公开(公告)号：WO2006002355A3
公开(公告)日：2007-01-11
申请号：PCT/US2005022422
申请日：2005-06-23
申请人： TERADYNE INC , NAKAMURA ATSUSHI
发明人： NAKAMURA ATSUSHI
IPC分类号： G01R19/00 , G01R19/04 , H03K5/153
CPC分类号： G01R19/04
摘要： A circuit and process for detecting peak-to-peak voltage are disclosed. The circuit comprises a first comparator having an output coupled to a first capacitor, a non-inverting input for receiving a high frequency AC waveform, and an inverting input, a second comparator having an output coupled to a second capacitor, and a first second input, an operational amplifier having a non-inverting input coupled to the inverting input of the first comparator, and an inverting input coupled to the first input. The process comprises charging a first capacitor when a high frequency AC waveform voltage is greater than a buffered voltage of the first capacitor, charging a second capacitor when an inverted buffered voltage of the second capacitor is greater than the high frequency AC waveform voltage, and outputting a voltage based on the buffered voltage of the first capacitor and the inverted buffered voltage of the second capacitor.
摘要翻译：公开了用于检测峰 - 峰电压的电路和工艺。该电路包括第一比较器，其具有耦合到第一电容器的输出端，用于接收高频AC波形的非反相输入端和反相输入端，具有耦合到第二电容器的输出的第二比较器和第一第二输入端，具有耦合到第一比较器的反相输入的非反相输入的运算放大器和耦合到第一输入的反相输入。该过程包括当高频AC波形电压大于第一电容器的缓冲电压时对第一电容器充电，当第二电容器的反相缓冲电压大于高频AC波形电压时，对第二电容器充电，并且输出基于第一电容器的缓冲电压和第二电容器的反相缓冲电压的电压。

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