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41. 发明申请

WO2018009154A1 RRAM DEVICES WITH EXTENDED SWITCHING LAYER AND METHODS OF FABRICATION 审中-公开
标题翻译：具有扩展开关层的RRAM器件和制造方法
公开(公告)号：WO2018009154A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040887
申请日：2016-07-02
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , KARPOV, Elijah V. , SHAH, Uday , MUKHERJEE, Niloy , MAJHI, Prashant , INDUKURI, Tejaswi K. , CLARKE, James S.
IPC分类号： H01L45/00
摘要： Approaches for integrating a switching layer that is continuous across an array of RRAM (RRAM) cells and the resulting structures, are described. In an example, a RRAM (RRAM) cell includes an RRAM device coupled to a conductive interconnect disposed in a dielectric layer above the substrate. An RRAM device includes a bottom electrode coupled to an oxygen exchange layer and a top electrode through a switching layer. The switching layer physically extends over the dielectric layer and the bottom electrodes associated with all RRAM devices in a given array. A dielectric spacer film is disposed on the sidewalls of the memory device extending from a lowermost portion of the oxygen exchange layer to the uppermost portion of the top electrode.
摘要翻译：描述了用于集成在RRAM（RRAM）单元阵列上连续的交换层和所得结构的方法。在一个示例中，RRAM（RRAM）单元包括耦合到设置在衬底上方的电介质层中的导电互连的RRAM器件。 RRAM器件包括通过开关层耦合到氧气交换层和顶部电极的底部电极。开关层物理地延伸在介电层和与给定阵列中的所有RRAM器件相关联的底部电极之上。电介质隔离膜设置在存储器件的侧壁上，从氧交换层的最低部分延伸到顶电极的最高部分。

42. 发明申请

WO2018004650A1 1T-1R RRAM CELL INCLUDING GROUP III-N ACCESS TRANSISTOR 审中-公开
标题翻译： 1T-1R RRAM单元，包括III-N族访问晶体管
公开(公告)号：WO2018004650A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040682
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , THEN, Han Wui , DASGUPTA, Sansaptak , KARPOV, Elijah V. , RADOSAVLJEVIC, Marko
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L29/0649 , H01L29/0847 , H01L29/2003 , H01L29/4236 , H01L29/7786 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： Techniques are disclosed for forming a one transistor, one resistor (1T-1R) resistive random-access memory (RRAM) cell including a group III-N access transistor, such as a gallium nitride (GaN) access transistor. Use of a group III-N access transistor in a 1T-1R RRAM cell enables relatively higher switching voltage and switching currents in a scaled RRAM cell as compared to conventional silicon (Si) access transistors. For example, for a given RRAM footprint, a 1T-1R configuration having a group III-N access transistor can achieve switching characteristics of almost double the amount of voltage and almost double the amount of current as compared to a 1T-1R configuration having a Si access transistor, with all else being the same. The relatively higher switching voltage/current at scaled dimensions enables the beneficial use of high voltage/high current switching film materials (e.g., tantalum oxide) for RRAM switching layers. Other embodiments may be described and/or disclosed.
摘要翻译：公开了用于形成包括诸如氮化镓（GaN）的III-N族存取晶体管的一个晶体管，一个电阻器（1T-1R）电阻式随机存取存储器（RRAM）单元的技术，存取晶体管。与常规硅（Si）存取晶体管相比，在1T-1R RRAM单元中使用III-N族存取晶体管可以在缩放的RRAM单元中实现相对较高的开关电压和开关电流。例如，对于给定的RRAM覆盖区，具有III-N族存取晶体管的1T-1R配置可以实现接近电压量的两倍的开关特性，并且与具有一个1T-1R配置的1T-1R配置 Si存取晶体管，其他都相同。尺寸缩小的相对较高的开关电压/电流使得RRAM开关层能够有益地使用高电压/高电流开关膜材料（例如氧化钽）。其他实施例可以被描述和/或公开。

43. 发明申请

WO2017052583A1 THERMALLY INSULATED RESISTIVE RANDOM ACCESS MEMORY 审中-公开
标题翻译：热绝缘电阻随机存取存储器
公开(公告)号：WO2017052583A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052198
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , SHAH, Uday , MAJHI, Prashant , MUKHERJEE, Niloy , PILLARISETTY, Ravi
IPC分类号： H01L27/115
CPC分类号： H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： An embodiment includes a resistive random access memory (RRAM) comprising: a top electrode portion and a bottom electrode portion; and an oxide layer between the top and bottom electrode portions; wherein (a) a conductive filament is within the oxide layer and is adjacent the top electrode portion, (b) the oxide layer includes oxide layer sidewalls, (c) a vertical axis intersects the oxide layer and the top and bottom electrode portions and is parallel to the oxide layer sidewalls, and (d) a void, which includes air, is adjacent the oxide layer sidewalls. Other embodiments are described herein.
摘要翻译：实施例包括电阻随机存取存储器（RRAM），其包括：顶部电极部分和底部电极部分; 以及在所述顶部和底部电极部分之间的氧化物层; 其中（a）导电丝在氧化物层的内部并与顶部电极部分相邻，（b）氧化物层包括氧化物层侧壁，（c）垂直轴与氧化物层和顶部和底部电极部分相交，并且是平行于氧化物层侧壁，和（d）包含空气的空隙与氧化物层侧壁相邻。本文描述了其它实施例。

44. 发明申请

WO2019132999A1 INTEGRATED CIRCUIT STRUCTURES WITH VERTICAL ARCHITECTURE 审中-公开
公开(公告)号：WO2019132999A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/069096
申请日：2017-12-29
申请人： INTEL CORPORATION
发明人： SHARMA, Abhishek A. , DOYLE, Brian S. , PILLARISETTY, Ravi , MAJHI, Prashant , KARPOV, Elijah V.
IPC分类号： H01L27/108 , H01L21/8234 , H01L21/768 , H01L21/02
摘要： Described herein are systems, methods, and apparatuses for vertical transistors for use in connection with memory devices. In an embodiment, in such a vertical transistor, the direction of current flow can be in a direction that is substantially perpendicular to the substrate on which the transistor is fabricated. In an embodiment, the current can flow from a source located at the top of the vertical transistor to a drain located at the bottom of the device, where the bottom of the vertical transistor is in proximity to the substrate on which the vertical transistor is fabricated. In another embodiment, the current can flow from a source located at the bottom of the vertical transistor to a drain located at the top of the device, where the bottom of the vertical transistor is in proximity to the substrate on which the vertical transistor is fabricated.

45. 发明申请

WO2019132995A1 SELECTORS FOR MEMORY DEVICES 审中-公开
公开(公告)号：WO2019132995A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/069092
申请日：2017-12-29
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , KARPOV, Elijah V. , MAJHI, Prashant , SHARMA, Abhishek A. , DOYLE, Brian S.
IPC分类号： H01L45/00 , H01L43/02
摘要： Disclosed herein are systems, methods, and apparatuses that are directed to a selector for use in connection with memory devices. In an embodiment, the selector can comprise a device that has current-voltage characteristics that are symmetric under opposing voltage biases. In an embodiment, the selector can be used in connection with a portion of a memory array, for example, in connection with wordlines and bitlines used in the memory array. In an embodiment, the selector can turn a memory device, for example, an resistive memory device such as an spin-transfer torque memory (STTM) device, on or off.

46. 发明申请

WO2019132994A1 MEMORY ARRAYS 审中-公开
公开(公告)号：WO2019132994A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/069090
申请日：2017-12-29
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , DOYLE, Brian S. , PILLARISETTY, Ravi , SHARMA, Abhishek , MAJHI, Prashant
IPC分类号： H01L27/11521 , H01L27/11526 , H01L27/11548 , H01L45/00 , H01L43/08
摘要： In an embodiment, described herein are systems, methods, and apparatuses directed towards segmentation of a large cross-point memory a memory array (or tile) into two or more memory arrays (sub-tiles) of smaller size for use as an embedded memory. In an embodiment, the memory array can be a three-dimensional x-point memory. In an embodiment, a portion of the memory can be segmented laterally, such that the sub-tiles are substantially arranged in a horizontal plane. In an embodiment, the sub-tiles can be fabricated in the same interconnect layer. In another embodiment, a portion of the memory can be segmented vertically, such that the sub-tiles are substantially arranged in a vertical plane.

47. 发明申请

WO2018063207A1 RESISTIVE RANDOM ACCESS MEMORY CELL 审中-公开
标题翻译：电阻式随机存取存储器单元
公开(公告)号：WO2018063207A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054299
申请日：2016-09-29
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , KARPOV, Elijah V. , MUKHERJEE, Niloy , CLARKE, James S. , PILLARISETTY, Ravi
IPC分类号： H01L45/00
摘要： Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a source junction, a gate, a drain junction, a semiconductor located below the gate and between the source junction and the drain junction, and an insulator located below the semiconductor. The semiconductor can be used to tune a terminal voltage (Vt). In an example, the semiconductor is an extremely thin silicon on an insulator. In another example, the semiconductor is a fully depleted silicon on insulator or an extremely thin silicon on an insulator.
摘要翻译：本文公开了用于启用电阻随机存取存储器单元的衬底，组件和技术。例如，在一些实施例中，器件可以包括源极结，栅极，漏极结，位于栅极下方以及源极结与漏极结之间的半导体以及位于半导体下方的绝缘体。半导体可以用来调整端电压（Vt）。在一个例子中，半导体是绝缘体上非常薄的硅。在另一个例子中，半导体是绝缘体上完全耗尽的硅或绝缘体上极薄的硅。

48. 发明申请

WO2018004625A1 CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY (CBRAM) DEVICES WITH ENGINEERED SIDEWALLS FOR FILAMENT LOCALIZATION 审中-公开
标题翻译：导电桥随机访问存储器（CBRAM）器件，带有工程设计的侧壁用于光纤本地化
公开(公告)号：WO2018004625A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040551
申请日：2016-06-30
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , KARPOV, Elijah V. , SHAH, Uday , PILLARISETTY, Ravi , MUKHERJEE, Niloy , BIELEFELD, Jeffery D. , INDUKURI, Tejaswi K. , CLARKE, James S.
IPC分类号： H01L45/00
CPC分类号： H01L45/00 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/16
摘要： Approaches for fabricating conductive bridge random access memory (CBRAM) devices with engineered sidewalls for filament localization, and the resulting structures and devices, are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes a first electrode layer disposed on the uppermost surface of the conductive interconnect. A resistance switching layer is disposed on the first electrode layer. The resistance switching layer includes an electrolyte material having doped regions at outermost ends of the electrolyte material but not in a central portion of the electrolyte material. A metal ion source layer is disposed on the resistance switching layer. A second electrode layer is disposed on the metal ion source layer.
摘要翻译：描述了用于制造具有用于灯丝定位的工程侧壁的导电桥随机存取存储器（CBRAM）器件以及所得到的结构和器件的方法。在一个示例中，导电桥随机存取存储器（CBRAM）器件包括设置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 CBRAM器件还包括布置在导电互连上的CBRAM元件。 CBRAM元件包括设置在导电互连的最上表面上的第一电极层。电阻切换层设置在第一电极层上。电阻切换层包括电解质材料，该电解质材料在电解质材料的最外端具有掺杂区域，但不在电解质材料的中心部分。金属离子源层设置在电阻切换层上。第二电极层设置在金属离子源层上。

49. 发明申请

WO2018004562A1 APPROACHES FOR FABRICATING SELF-ALIGNED PEDESTALS FOR RRAM DEVICES AND THE RESULTING STRUCTURES 审中-公开
标题翻译：用于制造RRAM器件自对准基座的方法及其结构
公开(公告)号：WO2018004562A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040030
申请日：2016-06-29
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , INDUKURI, Tejaswi K. , PILLARISETTY, Ravi , SHAH, Uday , MUKHERJEE, Niloy , KARPOV, Elijah V. , CLARKE, James S.
IPC分类号： G11C13/00 , H01L27/10 , H01L45/00
CPC分类号： H01L27/2436 , G11C13/0007 , G11C2213/15 , G11C2213/52 , G11C2213/79 , H01L45/00 , H01L45/08 , H01L45/1253 , H01L45/145 , H01L45/1675
摘要： Approaches for fabricating self-aligned pedestals for resistive random access memory (RRAM) elements and devices, and the resulting structures, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. An RRAM element is disposed on the conductive interconnect. The RRAM element includes a first electrode layer disposed on the conductive interconnect and in the ILD layer. The first electrode layer has an uppermost surface substantially co-planar with an uppermost surface of the ILD layer. A resistance switching layer is disposed on the uppermost surface of the first electrode layer and on a portion of the uppermost surface of the ILD layer. A second electrode layer is disposed on the resistance switching layer.
摘要翻译：描述了用于制造电阻随机存取存储器（RRAM）元件和器件的自对准基座以及所得到的结构的方法。在一个示例中，电阻随机存取存储器（RRAM）器件包括布置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 RRAM元件设置在导电互连上。 RRAM元件包括设置在导电互连上和ILD层中的第一电极层。第一电极层具有与ILD层的最上表面基本共面的最上表面。电阻切换层设置在第一电极层的最上表面上和ILD层的最上表面的一部分上。第二电极层设置在电阻切换层上。

50. 发明申请

WO2017171823A1 MULTILAYER SELECTOR DEVICE WITH LOW HOLDING VOLTAGE 审中-公开
标题翻译：具有低保持电压的多层选择器装置
公开(公告)号：WO2017171823A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025439
申请日：2016-03-31
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , PILLARISETTY, Ravi , MAJHI, Prashant , CLARKE, James S. , SHAH, Uday
IPC分类号： G11C13/00 , G11C11/16
CPC分类号： H01L43/02 , G11C11/161 , G11C11/1659 , G11C13/003 , G11C2213/76 , H01L27/228 , H01L43/10
摘要： An embodiment includes an apparatus comprising: a memory array comprising: a selector switch including top and bottom electrodes, a metal layer, and a solid electrolyte layer; a memory cell in series with the selector switch; bit and write lines, wherein (a)(i) the top electrode couples to one of the bit and write lines and the bottom electrode couples to another of the bit and write lines, and (a)(ii) the memory cell is between one of the top and bottom electrodes and one of the bit and write lines; wherein (b)(i) the metal layer includes silver (Ag), and (b)(ii) Ag ions from the metal layer form a conductive path in the SE layer when the top electrode is biased and disband the conductive path when the top electrode is not biased. Other embodiments are described herein.
摘要翻译：一个实施例包括一种装置，包括：存储器阵列，包括：选择器开关，包括顶部和底部电极，金属层和固体电解质层; 与选择器开关串联的存储器单元; 其中（a）（i）顶部电极耦合到位线和写入线中的一者，且底部电极耦合到位线和写入线中的另一者，且（a）（ii）存储器单元介于顶部和底部电极之一以及位线和写入线之一; 其中（b）（i）所述金属层包括银（Ag），和（b）（ii）当所述顶部电极被偏置时，来自所述金属层的Ag离子在所述SE层中形成导电路径，并且当上电极不偏置。这里描述了其他实施例。

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