专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

WO1997007594A1 PLL CIRCUIT AND PICTURE REPRODUCING DEVICE 审中-公开
标题翻译： PLL电路和图像再现设备
公开(公告)号：WO1997007594A1
公开(公告)日：1997-02-27
申请号：PCT/JP1996002190
申请日：1996-08-05
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM, LTD. , TAKAHASHI, Fumihiro , NACHI, Shikiko , YAMAMOTO, Norihisa , FURIHATA, Makoto
发明人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM, LTD.
IPC分类号： H03L07/08
CPC分类号： H03L7/0893 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/14 , H03L7/148 , H03L7/191 , H04N5/44504
摘要： A digital first phase comparator (22) and a sampling type second phase comparator (32) are provided in parallel. The output current Iout2 of the comparator (32) is inputted to a voltage-controlled oscillator (14) when the phase is close to a locked phase. In the other phase, the output current Iout1 of the comparator (22) is inputted to the oscillator (14). When part of a reference signal fs is lost, a complementing circuit (50) complements at least the reference signal fs inputted to the comparator (22) by pulses. A noise detecting and removing circuit (60) detects and removes the noise of the signal fs and inputs the signals fs to the comparators (22 and 32). The circuit (60) stops the operation of the comparators (22 and 32) for a prescribed period of time after detecting the noise. Therefore, the operation of a PLL circuit is stabilized and characters can be displayed sharply on a screen even when the horizontal synchronizing signal of video signals contains noise or part of the signal is lost.
摘要翻译：平行地提供数字第一相位比较器（22）和采样型第二相位比较器（32）。当相位接近锁定相位时，比较器（32）的输出电流Iout2被输入到压控振荡器（14）。在另一相位中，比较器（22）的输出电流Iout1输入到振荡器（14）。当参考信号fs的一部分丢失时，补充电路（50）至少补充了通过脉冲输入到比较器（22）的参考信号fs。噪声检测和去除电路（60）检测和去除信号fs的噪声，并将信号fs输入到比较器（22和32）。在检测到噪声之后，电路（60）停止比较器（22和32）的操作一段规定的时间。因此，即使当视频信号的水平同步信号包含噪声或部分信号丢失时，PLL电路的操作也能稳定地显示在屏幕上的字符。

32. 发明申请

WO1994024769A1 A PHASE LOCK LOOP WITH ERROR MEASUREMENT AND CORRECTION IN ALTERNATE PERIODS 审中-公开
标题翻译：具有错误测量和相对时间校正的相位锁定环
公开(公告)号：WO1994024769A1
公开(公告)日：1994-10-27
申请号：PCT/US1994004307
申请日：1994-04-19
申请人： RCA THOMSON LICENSING CORPORATION , SAUER, Donald, Jon , RODDA, William , CAMPBELL, Edward, Richard, III
发明人： RCA THOMSON LICENSING CORPORATION
IPC分类号： H03L07/113
CPC分类号： H03B5/24 , H03B5/20 , H03B2200/0038 , H03B2200/005 , H03B2200/0058 , H03B2201/02 , H03B2201/025 , H03B2201/0266 , H03J2200/10 , H03L7/099 , H03L7/0991 , H03L7/113 , H03L7/14 , H04N5/126 , H04N7/122
摘要： In a phase-lock-loop circuit a frequency detector measures a frequency error between an oscillatory signal and a synchronizing signal in alternate horizontal line periods for generating a frequency error indicative signal. The frequency error indicative signal is applied to an oscillator for correcting the frequency error in other alternate horizontal line periods in a manner to prevent frequency error measurement and correction from occurring in the same horizontal line period.
摘要翻译：在锁相环电路中，频率检测器在交替的水平行周期中测量振荡信号和同步信号之间的频率误差，以产生频率误差指示信号。频率误差指示信号被施加到用于校正其它交替水平行周期中的频率误差的振荡器，以防止频率误差测量和校正发生在相同的水平行周期中。

33. 发明申请

WO1986000768A1 DEVICE FOR TUNING A VCO TO THE CARRIER FREQUENCY OF EACH RADAR PULSE 审中-公开
标题翻译：用于调谐VCO到每个雷达脉冲的载波频率的装置
公开(公告)号：WO1986000768A1
公开(公告)日：1986-01-30
申请号：PCT/IT1985000014
申请日：1985-07-03
申请人： SELENIA, INDUSTRIE ELETTRONICHE ASSOCIATE , MASDEA, Arturo , BARTOLINI, Pietro , COLAVITO, Gianfranco , NERI, Filippo
发明人： SELENIA, INDUSTRIE ELETTRONICHE ASSOCIATE
IPC分类号： H03L07/14
CPC分类号： G01S7/28 , H03L7/087 , H03L7/14
摘要： Electronic device for rapidly tuning a voltage controlled oscillator to the radar carrier frequency of each of the individual radar pulses. A frequency discriminator (1) of the quadricorrelator type is supplied with the incoming pulses and with the output of the VCO (5) to provide the control voltage to the VCO (5) via amplifying stages (2), (4) and a sample-and-hold circuit (3) that maintains the tuned frequency for time durations greater than 100 mu sec. The operating frequency range of the device is between 6GHz - 18 GHz.
摘要翻译：用于将压控振荡器快速调谐到每个雷达脉冲的雷达载波频率的电子设备。四通道相关器类型的鉴频器（1）被提供有输入脉冲和VCO（5）的输出，以通过放大级（2），（4）和样本（5）向VCO（5）提供控制电压保持电路（3），其保持调谐频率大于100μsec的持续时间。器件的工作频率范围在6GHz至18GHz之间。

34. 发明申请

WO1981001782A1 CRYSTAL-OSCILLATOR-STABILIZED PHASE-LOCKED-LOOP-CIRCUIT 审中-公开
标题翻译：晶体振荡器稳定的相位锁定环路
公开(公告)号：WO1981001782A1
公开(公告)日：1981-06-25
申请号：PCT/US1980001594
申请日：1980-12-01
申请人： GENERAL ELECTRIC CO
发明人： GENERAL ELECTRIC CO , HUGHES W , HACKERT W
IPC分类号： H03L07/10
CPC分类号： H03L7/185 , H03L7/10 , H03L7/14 , Y10S331/02
摘要： A phase-locked loop circuit, having an oscillator (15) controlled by a voltage (VO') related to phase difference between a reference signal (fL) and a loop signal (fL'), is stabilized by a crystal oscillator (18). The voltage controlled oscillator signal (f1) is frequency-substracted from the crystal oscillator signal frequency (fx) to provide an input signal (fS) to a frequency-arithmetic synthesizer (21) which provides the loop signal (fL') to the phase detector (12) for comparison with the coming reference signal. Use of a frequency-adder circuit between the voltage controlled oscillator (15) and the frequency-subtractor (16) and receiving an addition frequency derived from the frequency-arithmetic synthesizing circuit (21) is utilized to decrease the loop gain and provide enhanced characteristics.

35. 发明申请

WO2016093004A1 基準信号発生装置审中-公开
标题翻译：标准信号发生装置
公开(公告)号：WO2016093004A1
公开(公告)日：2016-06-16
申请号：PCT/JP2015/081577
申请日：2015-11-10
申请人：古野電気株式会社
发明人：橋本　邦彦
IPC分类号： H03L7/14
CPC分类号： H03L7/0992 , H03L7/0805 , H03L7/0807 , H03L7/091 , H03L7/14 , H03L7/143 , H03L7/189 , H04L7/04
摘要：【課題】リファレンス信号と同期した信号を得るために、デジタル信号をアナログ信号に変換して電圧制御発振器に与えて制御する同期回路を備えた基準信号発生装置において、リファレンス信号を取得できないホールドオーバー制御時の量子化誤差の累積の問題を解決する。【解決手段】基準周波数発生装置１０は、位相同期回路２５と、制御部１１と、を備える。位相同期回路２５は、リファレンス信号に基づいて得られた制御信号によって、発振部２７が出力する基準信号を制御する。制御部１１は、リファレンス信号を取得できなくなると、自走用制御信号を生成して発振部２７を制御する。発振部２７は、入力された離散値に応じて発振する。制御部１１の後段には、制御部１１の自走用制御信号を変調するデジタル型のデルタシグマ変調器１５が配置される。
摘要翻译：本发明解决了在具有通过将数字信号转换成模拟信号来进行控制的同步电路的标准信号发生装置中，当不能获取参考信号时，在保持控制期间的量化误差累积的问题以及将所述模拟信号提供给压控振荡器，以获得与参考信号同步的信号。 [解决方案]标准频率发生装置10具有相位同步电路25和控制单元11.相位同步电路25通过基于以下方式获得的控制信号来控制由振荡单元27输出的标准信号：参考信号。如果不可能获取参考信号，则控制单元11通过产生用于自行进的控制信号来控制振荡单元27。振荡单元27根据输入的离散值而振荡。从控制单元11调制用于自行进的控制信号的数字Δ-Σ调制器15设置在控制单元11的下游。

36. 发明申请

WO2007037991A3 TRI-STATING A PHASE LOCKED LOOP TO CONSERVE POWER 审中-公开
标题翻译：确定相位锁定环以保持功率
公开(公告)号：WO2007037991A3
公开(公告)日：2007-10-18
申请号：PCT/US2006035778
申请日：2006-09-12
申请人： CYPRESS SEMICONDUCTOR CORP , GEHRING MARK R , MOYAL NATHAN
发明人： GEHRING MARK R , MOYAL NATHAN
IPC分类号： H03L7/00
CPC分类号： H03L7/0802 , H03L7/0891 , H03L7/14 , H03L7/18
摘要： In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.
摘要翻译：在具有间歇操作无线电的系统中，其频率由锁相环（PLL）控制，该方法和系统通过在PLL之后三态PLL中的控制电容来降低由PLL消耗的功率以设计频率稳定。电容器稳定后，PLL中某些组件的供电会减少。

37. 发明申请

WO2003041276A2 CASCADED DELAY LOCKED LOOP CIRCUIT 审中-公开
标题翻译： CASCADED延迟锁定环路
公开(公告)号：WO2003041276A2
公开(公告)日：2003-05-15
申请号：PCT/US2002/033935
申请日：2002-10-23
申请人： MOTOROLA, INC.
发明人： JUAN, Jui-Kuo , STENGEL, Robert, E. , MARTIN, Frederick, L. , BOCKELMAN, David, E.
IPC分类号： H03L
CPC分类号： H03L7/16 , H03L7/07 , H03L7/0812 , H03L7/14 , H03L2207/08
摘要： A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.
摘要翻译：在几个实施例中，延迟锁定环频率合成器使用主延迟线元件（24）和一个或多个辅助延迟元件（162 164,270,310）。在一个实施例中，主延迟线（24）用于粗略地选择频率输出，而使用无源或有源的辅助延迟元件（162 164,270,310）来增加主延迟线的分辨率 24）。在被动实施例中，通过从主延迟线（24）的输出抽头中选择分量作为被动次级延迟元件（310）的驱动信号来提供粗调和选择输出，可以进行粗略和精细的频率选择从第二延迟元件（310）提供精细选择。

38. 发明申请

WO0209290A3 ANALOG PHASE LOCKED LOOP HOLDOVER 审中-公开
标题翻译：模拟相锁定环保持器
公开(公告)号：WO0209290A3
公开(公告)日：2002-08-15
申请号：PCT/US0120936
申请日：2001-07-02
申请人： MARCONI COMM INC
发明人： BEAULIEU REJEAN
IPC分类号： H03L7/089 , H03L7/14 , H03L7/18
CPC分类号： H03L7/089 , H03L7/14 , H03L7/146 , H03L7/18
摘要： A phase locked loop (PLL) circuit is provided having: (1) a phase detector coupled to a reference clock signal and a feedback signal for generating positive and negative phase detection signals corresponding to the phase difference between the reference clock signal and the feedback signal; (2) an integrator coupled to the positive and negative phase detection signals for generating an output voltage proportional to the pulse width of either the positive or negative phase detection signals, the integrator including an operational amplifier having positive and negative inputs; (3) a voltage controlled oscillator coupled to the output voltage of the integrator for generating a local oscillator signal with an oscillation frequency proportional to the output voltage of the integrator; (4) a feedback circuit coupled to the local oscillator signal for generating the feedback signal; and (5) an analog holdover circuit for generating an input to the integrator when the phase detector stops receiving the reference clock signal.
摘要翻译：提供锁相环（PLL）电路，其具有：（1）耦合到参考时钟信号和反馈信号的相位检测器，用于产生对应于参考时钟信号和反馈信号之间的相位差的正相位和负相位检测信号 ; （2）耦合到正相和负相检测信号的积分器，用于产生与正或负相位检测信号的脉冲宽度成比例的输出电压，积分器包括具有正和负输入的运算放大器; （3）耦合到积分器的输出电压的压控振荡器，用于产生具有与积分器的输出电压成比例的振荡频率的本地振荡器信号; （4）耦合到本地振荡器信号的反馈电路，用于产生反馈信号; （5）一个模拟保持电路，用于当相位检测器停止接收参考时钟信号时产生到积分器的输入。

39. 发明申请

WO02009290A2 ANALOG PHASE LOCKED LOOP HOLDOVER 审中-公开
标题翻译：模拟锁相环锁定
公开(公告)号：WO02009290A2
公开(公告)日：2002-01-31
申请号：PCT/US2001/020936
申请日：2001-07-02
IPC分类号： H03L7/089 , H03L7/14 , H03L7/18 , H03L7/00
CPC分类号： H03L7/089 , H03L7/14 , H03L7/146 , H03L7/18
摘要： A phase locked loop (PLL) circuit is provided having: (1) a phase detector coupled to a reference clock signal and a feedback signal for generating positive and negative phase detection signals corresponding to the phase difference between the reference clock signal and the feedback signal; (2) an integrator coupled to the positive and negative phase detection signals for generating an output voltage proportional to the pulse width of either the positive or negative phase detection signals, the integrator including an operational amplifier having positive and negative inputs; (3) a voltage controlled oscillator coupled to the output voltage of the integrator for generating a local oscillator signal with an oscillation frequency proportional to the output voltage of the integrator; (4) a feedback circuit coupled to the local oscillator signal for generating the feedback signal; and (5) an analog holdover circuit for generating an input to the integrator when the phase detector stops receiving the reference clock signal.
摘要翻译：提供了一种锁相环（PLL）电路，其具有：（1）耦合到参考时钟信号的相位检测器和用于产生对应于参考时钟信号和反馈信号之间的相位差的正和负相位检测信号的反馈信号 ; （2）积分器，耦合到正和负相位检测信号，用于产生与正或负相位检测信号的脉冲宽度成比例的输出电压，积分器包括具有正和负输入的运算放大器; （3）耦合到积分器的输出电压的压控振荡器，用于产生具有与积分器的输出电压成比例的振荡频率的本地振荡器信号; （4）耦合到本地振荡器信号的反馈电路，用于产生反馈信号; 和（5）模拟保持电路，用于当相位检测器停止接收参考时钟信号时，产生对积分器的输入。

40. 发明申请

WO01086815A2 METHOD AND APPARATUS FOR REDUCING PLL LOCK TIME 审中-公开
标题翻译：减少PLL锁定时间的方法和装置
公开(公告)号：WO01086815A2
公开(公告)日：2001-11-15
申请号：PCT/US2001/014992
申请日：2001-05-08
IPC分类号： H03L7/10 , H03L7/08 , H03L7/14 , H03L7/18 , H03L7/187 , H03L7/00
CPC分类号： H03L7/14 , H03L7/0802 , H03L7/18 , H03L2207/08 , H03L2207/18
摘要： The lock time is reduced in a phase locked loop frequency synthesizer that has both active modes and standby modes. In the active mode the frequency synthesizer operates to maintain a stable frequency output. The standby or sleep mode is used to reduce power consumption when the frequency synthesizer is not required to provide a frequency output. When the synthesizer is placed in standby mode the most recent value of the Voltage Controlled Oscillator (VCO) tuning voltage is maintained on the VCO tuning control line of the frequency synthesizer. The voltage is maintained on the VCO tuning output pin in Integrated Circuit (IC) frequency synthesizers. The voltage error on the VCO tuning pin is minimized thereby minimizing the lock time of the frequency synthesizer.
摘要翻译：锁相环频率合成器的锁定时间减少，同时具有两种工作模式和待机模式。在激活模式下，频率合成器运行以保持稳定的频率输出。当频率合成器不需要提供频率输出时，待机或睡眠模式用于降低功耗。当合成器处于待机模式时，压控振荡器（VCO）调谐电压的最新值保持在频率合成器的VCO调谐控制线上。在集成电路（IC）频率合成器中的VCO调谐输出引脚上保持电压。 VCO调谐引脚上的电压误差最小化，从而将频率合成器的锁定时间最小化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式