专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

WO2009012276A3 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 审中-公开
标题翻译：非对称场效应晶体管结构与方法
公开(公告)号：WO2009012276A3
公开(公告)日：2009-03-26
申请号：PCT/US2008070102
申请日：2008-07-16
申请人： IBM , ANDERSON BRENT A , BRYANT ANDRES , CLARK WILLIAM F , NOWAK EDWARD J
发明人： ANDERSON BRENT A , BRYANT ANDRES , CLARK WILLIAM F , NOWAK EDWARD J
IPC分类号： H01L21/335
CPC分类号： H01L29/78 , H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure (200a-c) and a method of forming the structure in which both series resistance in the source region (204, 304) (Rs) and gate (210, 310) to drain ((205, 305) capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay) Specifically, different heights (214, 215) of the source (204) and drain regions (205) and/or different distances (351, 352) between the source (304) and drain regions (305) and the gate (210, 310) are tailored to minimize series resistance in the source region (204, 305) (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate (210, 310) to drain (205, 305) capacitance (i.e., in order to simultaneously ensure that gate ( 210, 310) to drain (205, 305) capacitance is less than a predetermined capacitance value).
摘要翻译：公开了不对称场效应晶体管结构（200a-c）的实施例以及形成其中源极区（204,304）（Rs）和栅极（210,310）中的两个串联电阻漏极（（（204）和漏极区域（205）的不同高度（214,215），以便提供最佳性能（即，提供具有最小电路延迟的改进的驱动电流）和/或源极（304）和漏极区域（305）与栅极（210,310）之间的不同距离（351,352）被调整为使源极区域（204,305）中的串联电阻最小化（即，按顺序以确保串联电阻小于预定电阻值）并且为了同时使栅极（210,310）与漏极（205,305）的电容最小化（即，为了同时确保栅极（210,310）至漏极（205,305）电容小于预定电容值）。

32. 发明申请

WO2009030165A1 LDMOS及集成LDMOS与CMOS的半导体器件审中-公开
公开(公告)号：WO2009030165A1
公开(公告)日：2009-03-12
申请号：PCT/CN2008/072196
申请日：2008-08-29
申请人：谭健
发明人：谭健
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0922 , H01L21/823814 , H01L21/823892 , H01L29/1083 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7833 , H01L29/7835
摘要： An LDMOS is provided, which includes a channel on the surface of a semiconductor substrate, a gate electrode over the channel, and a source or drain with a heavily doped region and a lightly doped region which is adjacent to the channel and the heavily doped region closely. The LDMOS also includes an inversely doped well with dopant type contrary to that of the source or drain and an inversely doped region with dopant type contrary to that of the source or drain. The inversely doped well is beneath the channel and embracing the channel, and the inversely doped region is positioned between the heavily doped region and the inversely doped well. A semiconductor device integrated with LDMOS and CMOS is also provided.

33. 发明申请

WO2009020512A1 INTEGRATED CIRCUIT FABRICATION PROCESS USING A COMPRESSION CAP LAYER IN FORMING A SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION 审中-公开
标题翻译：集成电路制造工艺使用压缩层形成硅胶，具有最小的后激光退火猝死
公开(公告)号：WO2009020512A1
公开(公告)日：2009-02-12
申请号：PCT/US2008/008711
申请日：2008-07-16
申请人： APPLIED MATERIALS, INC.
发明人： MA, Yi , KRAUS, Philip, Allan , OLSEN, Christopher, Sean , AHMED, khaled, Z. , MAYUR, Abhilash, J.
IPC分类号： B23K26/02 , H01L21/02
CPC分类号： B23K26/0738 , B23K26/082 , B23K26/0876 , H01L21/268 , H01L21/28518 , H01L21/76828 , H01L29/665
摘要： Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying compression cap layer, to prevent metal agglomeration at the silicon melting temperature. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing near the silicon melting temperature.
摘要翻译：通过在激光退火之前执行特定的硅化物形成工艺步骤，使激光后退火掺杂剂失活最小化。在源极 - 漏极区域和栅极电极上沉积贱金属层，随后沉积上覆的压缩覆盖层，以防止在硅熔融温度下的金属聚集。此后，进行快速热处理以充分加热衬底，以在源极 - 漏极区域和栅电极的顶表面处形成金属硅化物接触。该方法还包括去除剩余的含金属层，然后在靠近硅熔化温度的激光退火之前，在衬底上沉积光吸收层。

34. 发明申请

WO2009020511A1 INTEGRATED CIRCUIT FABRICATION PROCESS FOR A HIGH MELTING TEMPERATURE SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION 审中-公开
标题翻译：用于具有最小激光退火猝死活性的高熔点温度硅胶的集成电路制造工艺
公开(公告)号：WO2009020511A1
公开(公告)日：2009-02-12
申请号：PCT/US2008/008710
申请日：2008-07-16
申请人： APPLIED MATERIALS, INC.
发明人： MA, Yi , KRAUS, Philip, Allan , OLSEN, Christopher, Sean , AHMED, Khaled, Z. , MAYUR, Abhilash, J.
IPC分类号： B23K26/02 , H01L21/02
CPC分类号： B23K26/0738 , B23K26/082 , B23K26/0876 , H01L21/268 , H01L29/665
摘要： Post-laser annealing dopant deactivation is minimized by performing certain suicide formation process steps prior to laser annealing. A base metal layer of nickel is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying layer of a metal having a higher melting temperature than nickel. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal suicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing.
摘要翻译：通过在激光退火之前执行特定的硅化物形成工艺步骤，使激光后退火掺杂剂失活最小化。在源 - 漏区和栅电极上沉积镍的贱金属层，然后沉积具有比镍更高的熔融温度的金属的上覆层。此后，进行快速热处理以充分加热衬底，以在源极 - 漏极区域和栅极电极的顶表面处形成金属硅化物接触。该方法还包括去除剩余的含金属层，然后在激光退火之前在衬底上沉积光吸收层。

35. 发明申请

WO2008147608A1 SEMICONDUCTOR DEVICE WITH STRESSORS AND METHODS THEREOF 审中-公开
标题翻译：具有抗压件的半导体器件及其方法
公开(公告)号：WO2008147608A1
公开(公告)日：2008-12-04
申请号：PCT/US2008/061268
申请日：2008-04-23
申请人： FREESCALE SEMICONDUCTOR INC. , ZOLLNER, Stefan , DHANDAPANI, Veeraraghavan , GRUDOWSKI, Paul A.
发明人： ZOLLNER, Stefan , DHANDAPANI, Veeraraghavan , GRUDOWSKI, Paul A.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66628 , H01L21/26506 , H01L29/665 , H01L29/66772 , H01L29/7843
摘要： A semiconductor device (10) is formed in a semiconductor layer (16). A gate dielectric (20) is formed over a top surface of the semiconductor layer (16). A gate stack (18) is over the gate dielectric (20). A sidewall spacer (24) is formed around the gate stack (18). Using the sidewall spacer (24) as a mask, an implant is performed to form deep source/drain regions (28, 30) in the semiconductor layer. Silicon carbon regions (32, 36, 34) are formed on the deep source/drain regions (28, 30) and a top surface of the gate stack. The silicon carbon regions (32, 34, 36) are silicided with nickel.
摘要翻译：半导体器件（10）形成在半导体层（16）中。栅电介质（20）形成在半导体层（16）的顶表面上。栅极堆叠（18）位于栅极电介质（20）的上方。在栅极堆叠（18）周围形成侧壁间隔物（24）。使用侧壁间隔件（24）作为掩模，执行注入以在半导体层中形成深源极/漏极区域（28,30）。在深源/漏区（28,30）和栅叠层的顶表面上形成硅碳区（32,36,34）。硅碳区域（32,34,36）用镍硅化。

36. 发明申请

WO2008106397A3 PROCESS METHOD TO OPTIMIZE FULLY SILICIDED GATE (FUSI) THRU PAI IMPLANT 审中-公开
标题翻译：优化完全硅酸盐（FUSI）THRU PAI IMPLANT的工艺方法
公开(公告)号：WO2008106397A3
公开(公告)日：2008-11-27
申请号：PCT/US2008054872
申请日：2008-02-25
申请人： TEXAS INSTRUMENTS INC , JOHNSON FRANK SCOTT , MEHRAD FREIDOON , LU JIONG-PING
发明人： JOHNSON FRANK SCOTT , MEHRAD FREIDOON , LU JIONG-PING
IPC分类号： H01L21/425 , H01L29/94
CPC分类号： H01L21/28097 , H01L21/26506 , H01L29/4975 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： An improved method of forming a fully suicided (FUSI) gate (2) in both NMOS and PMOS transistors (1) of the same MOS device is disclosed. In one example, the method comprises forming oxide and nitride etch-stop layers over a top portion of the gates of the NMOS and PMOS transistors, forming a blocking layer over the etch- stop layer, planarizing the blocking layer down to the etch- stop layer over the gates, and removing a portion of the etch-stop layer overlying the gates. The method further includes implanting a preamorphizing species into the exposed gates to amorphize the gates, thereby permitting uniform suicide formation thereafter at substantially the same rates in the NMOS and PMOS transistors. The method may further comprise removing any remaining oxide or blocking layers, forming the gate suicide (4) over the gates to form the FUSI gates, and forming source/drain suicide (5) in moat areas of the NMOS and PMOS transistors.
摘要翻译：公开了在相同MOS器件的NMOS和PMOS晶体管（1）中形成完全自杀（FUSI）栅极（2）的改进方法。在一个示例中，该方法包括在NMOS和PMOS晶体管的栅极的顶部部分上形成氧化物和氮化物蚀刻停止层，在蚀刻停止层上形成阻挡层，将阻挡层平坦化到蚀刻停止并且去除覆盖在栅极上的蚀刻停止层的一部分。该方法还包括将预变质物质植入暴露的栅极以使栅极非晶化，从而在NMOS和PMOS晶体管中以基本上相同的速率允许其后形成均匀的硅化物形成。该方法可以进一步包括去除任何剩余的氧化物或阻挡层，在栅极上形成栅极硅化物（4）以形成FUSI栅极，以及在NMOS和PMOS晶体管的护环区域中形成源极/漏极硅化物（5）。

37. 发明申请

WO2008137480A2 ACTIVE AREA JUNCTION ISOLATION STRUCTURE AND JUNCTION ISOLATED TRANSISTORS INCLUDING IGFET, JFET AND MOS TRANSISTORS AND METHOD FOR MAKING 审中-公开
标题翻译：具有IGFET，JFET和MOS晶体管的主动区隔离结构和结隔离晶体管及其制造方法
公开(公告)号：WO2008137480A2
公开(公告)日：2008-11-13
申请号：PCT/US2008/062101
申请日：2008-04-30
申请人： DSM SOLUTIONS, INC. , VORA, Madhukar, B.
发明人： VORA, Madhukar, B.
IPC分类号： H01L21/761
CPC分类号： H01L29/808 , H01L21/28525 , H01L21/761 , H01L21/76895 , H01L21/8213 , H01L21/823481 , H01L21/823878 , H01L29/1066 , H01L29/665 , H01L29/7833
摘要： Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and wells so bias voltages applied to reverse bias PN junctions to isolate active areas. Insulating layer is formed on top surface of substrate and interconnect channels are etched in insulating layer which do not go down to the semiconductor substrate. Contact openings for surface contacts to wells and substrate are etched in insulating layer down to semiconductor layer. Doped silicon or metal is formed in contact openings for surface contacts and to form interconnects in channels. Silicide may be formed on top of polycrystalline silicon contacts and interconnect lines to lower resistivity. Any JFET or MOS transistor may be integrated into the resulting junction isolated active area.
摘要翻译：用于晶体管的集成有源区隔离结构来代替更大和更昂贵的浅沟槽隔离或场氧化物来隔离晶体管。在井之间形成PN结，并且与衬底和阱的表面接触形成多阱注入，因此施加到反向偏置PN结的偏置电压以隔离有源区。绝缘层形成在衬底的顶表面上，互连通道被蚀刻在绝缘层中，绝缘层不会下降到半导体衬底。用于与阱和衬底的表面接触的接触开口在绝缘层中被蚀刻到半导体层。掺杂的硅或金属形成在用于表面接触的接触开口中并且在通道中形成互连。可以在多晶硅触点和互连线之上形成硅化物以降低电阻率。任何JFET或MOS晶体管可以集成到所得到的结隔离有源区域中。

38. 发明申请

WO2008130598A1 MOS TRANSISTORS HAVING HIGH-K OFFSET SPACERS THAT REDUCE EXTERNAL RESISTANCE AND METHODS FOR FABRICATING THE SAME 审中-公开
标题翻译：具有降低外部电阻的高K偏置间隔的MOS晶体管及其制造方法
公开(公告)号：WO2008130598A1
公开(公告)日：2008-10-30
申请号：PCT/US2008/004963
申请日：2008-04-17
申请人： ADVANCED MICRO DEVICES, INC. , YANG, Frank, Bin , HARGROVE, Michael
发明人： YANG, Frank, Bin , HARGROVE, Michael
IPC分类号： H01L21/336 , H01L21/28 , H01L29/49 , H01L29/51
CPC分类号： H01L21/28114 , H01L21/26513 , H01L29/4983 , H01L29/512 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： MOS transistors (102, 202) having high-k spacers (118) and methods for fabricating such transistors are provided. One exemplary method comprises forming a gate stack (134) overlying a semiconductor substrate (104) and forming an offset spacer (118) about sidewalls (122) of the gate stack (134). The offset spacer (118) is formed of a high-k dielectric material that results in a low interface trap density between the offset spacer (118) and the semiconductor substrate (104). First ions (138) of a conductivity-determining impurity type are implanted into the semiconductor substrate (104) using the gate stack (134) and the offset spacer (118) as an implantation mask to form spaced- apart impurity- doped extensions (112).
摘要翻译：提供了具有高k间隔物（118）的MOS晶体管（102,202）以及制造这种晶体管的方法。一个示例性方法包括形成覆盖半导体衬底（104）的栅极叠层（134）并且在栅叠层（134）的侧壁（122）周围形成偏移间隔物（118）。偏移间隔物（118）由高k电介质材料形成，其导致偏移间隔物（118）和半导体衬底（104）之间的低界面陷阱密度。使用栅极堆叠（134）和偏移间隔物（118）作为注入掩模将导电性确定杂质类型的第一离子（138）注入到半导体衬底（104）中以形成间隔开的杂质掺杂延伸部）。

39. 发明申请

WO2008106397A2 PROCESS METHOD TO OPTIMIZE FULLY SILICIDED GATE (FUSI) THRU PAI IMPLANT 审中-公开
标题翻译：优化全硅化门（FUSI）直通PAI植入物的工艺方法
公开(公告)号：WO2008106397A2
公开(公告)日：2008-09-04
申请号：PCT/US2008/054872
申请日：2008-02-25
申请人： TEXAS INSTRUMENTS INCORPORATED , JOHNSON, Frank, Scott , MEHRAD, Freidoon , LU, Jiong-Ping
发明人： JOHNSON, Frank, Scott , MEHRAD, Freidoon , LU, Jiong-Ping
IPC分类号： H01L21/3205
CPC分类号： H01L21/28097 , H01L21/26506 , H01L29/4975 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： An improved method of forming a fully suicided (FUSI) gate (2) in both NMOS and PMOS transistors (1) of the same MOS device is disclosed. In one example, the method comprises forming oxide and nitride etch-stop layers over a top portion of the gates of the NMOS and PMOS transistors, forming a blocking layer over the etch- stop layer, planarizing the blocking layer down to the etch- stop layer over the gates, and removing a portion of the etch-stop layer overlying the gates. The method further includes implanting a preamorphizing species into the exposed gates to amorphize the gates, thereby permitting uniform suicide formation thereafter at substantially the same rates in the NMOS and PMOS transistors. The method may further comprise removing any remaining oxide or blocking layers, forming the gate suicide (4) over the gates to form the FUSI gates, and forming source/drain suicide (5) in moat areas of the NMOS and PMOS transistors.
摘要翻译：公开了在同一MOS器件的NMOS和PMOS晶体管（1）中形成完全硅化（FUSI）栅极（2）的改进方法。在一个实例中，该方法包括在NMOS和PMOS晶体管的栅极的顶部上方形成氧化物和氮化物蚀刻停止层，在蚀刻停止层上方形成阻挡层，将阻挡层平坦化到蚀刻停止在栅极上方形成一层，并去除覆盖在栅极上的一部分蚀刻停止层。该方法进一步包括将预变形物质植入暴露的栅极中以非晶化栅极，由此允许在NMOS和PMOS晶体管中以基本相同的速率形成均匀的硅化物。该方法还可以包括去除任何剩余的氧化物或阻挡层，在栅极上方形成栅极硅化物（4）以形成FUSI栅极，以及在NMOS和PMOS晶体管的沟槽区域中形成源极/漏极硅化物（5） p>

40. 发明申请

WO2008103791A1 FORMATION OF A SELECTIVE CARBON-DOPED EPITAXIAL CAP LAYER ON SELECTIVE EPITAXIAL SIGE 审中-公开
标题翻译：在选择性外源信号上形成选择性碳掺杂的外延层
公开(公告)号：WO2008103791A1
公开(公告)日：2008-08-28
申请号：PCT/US2008/054521
申请日：2008-02-21
申请人： TEXAS INSTRUMENTS INCORPORATED , WEIJTMANS, Johan , LU, Jiong-Ping , WISE, Rick
发明人： WEIJTMANS, Johan , LU, Jiong-Ping , WISE, Rick
IPC分类号： H01L21/00 , H01L27/06
CPC分类号： H01L29/7834 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer (10) having a PMOS transistor gate stack, extension sidewalls (130), source/drain extension regions (70), and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region (150) coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.
摘要翻译：一种用于形成PMOS晶体管的外延SiGe的方法。在示例性实施例中，该方法可以包括提供具有PMOS晶体管栅极堆叠，延伸侧壁（130），源极/漏极延伸区域（70）和有源区域的半导体晶片（10）。该方法还可以包括通过形成耦合到凹入的有源区域的表面的选择性外延SiGe区域（150）和选择性碳掺杂的外延盖层（150），在有源区域内执行凹陷蚀刻并在凹入的有源区域内形成外延SiGe 耦合到选择性epi SiGe区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式