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31. 发明申请

WO2015021257A1 N-PHASE SIGNAL TRANSITION ALIGNMENT 审中-公开
标题翻译： N相信号转换对准
公开(公告)号：WO2015021257A1
公开(公告)日：2015-02-12
申请号：PCT/US2014/050108
申请日：2014-08-07
申请人： QUALCOMM INCORPORATED
发明人： LEE, Chulkyu , WILEY, George Alan
IPC分类号： G06F13/42 , H04L25/49
CPC分类号： G06F13/36 , G06F13/4063 , G06F13/4068 , G06F13/4278 , G06F13/4282 , H04L7/0033 , H04L25/14 , H04L25/4917 , H04L25/4919 , Y02D10/14 , Y02D10/151
摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state.
摘要翻译：描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。信息以N相极性编码符号发送。驱动器可以被适配或配置成在两个或更多个连接器上对准状态转换，以使连续符号之间的过渡周期最小化。驱动器可以包括推进或延迟某些转换的电路。驱动器可以包括预加重电路，即，即使当连接器转换到未驱动状态时，该预加重电路用于驱动连接器的一部分过渡期的状态。

32. 发明申请

WO2014138646A1 VOLTAGE MODE DRIVER CIRCUIT FOR N-PHASE SYSTEMS 审中-公开
标题翻译：用于N相系统的电压模式驱动电路
公开(公告)号：WO2014138646A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/021994
申请日：2014-03-07
申请人： QUALCOMM INCORPORATED
发明人： LEE, Chulkyu , WILEY, George Alan , SENGOKU, Shoichiro
IPC分类号： G06F13/40
CPC分类号： H04B3/06 , G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. Each of the three terminals may be driven such that transistors are activated to couple a terminal to first and second voltage levels through a pair of impedances when the terminal would otherwise be undriven. The terminal is then pulled toward an intermediate voltage level while the terminal presents a desired impedance level to a transmission line.
摘要翻译：描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。当传输线否则将被驱动时，传输线选择性地终止在N相极性编码的发射机中。数据被映射到要在多根线上传输的符号序列。符号序列被编码为三个信号。可以驱动三个端子中的每一个，使得晶体管被激活以在端子否则将不被引导时通过一对阻抗将端子耦合到第一和第二电压电平。然后将终端拉向中间电压电平，同时终端向传输线呈现期望的阻抗电平。

33. 发明申请

WO2014005117A1 N-PHASE POLARITY OUTPUT PIN MODE MULTIPLEXER 审中-公开
标题翻译： N相极性输出引脚模式多路复用器
公开(公告)号：WO2014005117A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/048758
申请日：2013-06-28
申请人： QUALCOMM INCORPORATED
发明人： WILEY, George Alan , RASKIN, Glenn D. , LEE, Chulkyu
IPC分类号： H04L25/02
CPC分类号： H04L25/02 , G06F13/385 , H04L5/1423 , H04L5/16 , H04L25/0272 , H04L25/14 , H04L25/4923 , H04L25/493
摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N -phase polarity encoded symbols or as packets on differentially driven connectors. A desired operational mode for communicating between the two devices is determined, an encoder is selected to drive a plurality of connectors communicatively coupling the two devices, and a plurality of drivers is configured to receive encoded data from the encoder and drive the plurality of connectors. Switches may couple outputs of the selected encoder to the plurality of drivers. One or more outputs of another encoder may be caused or forced to enter a high impedance mode.
摘要翻译：描述了促进数据传输的系统，方法和设备，特别是在电子设备内的两个设备之间传输数据。数据被选择性地作为N相极性编码符号或作为差分驱动连接器上的分组传送。确定用于在两个设备之间进行通信的期望操作模式，选择编码器以驱动可通信地耦合两个设备的多个连接器，并且多个驱动器被配置为从编码器接收编码数据并驱动多个连接器。开关可以将所选编码器的输出耦合到多个驱动器。另一个编码器的一个或多个输出可能会导致或被迫进入高阻抗模式。

34. 发明申请

WO2023038737A1 CLOCK AND DATA RECOVERY FOR MULTI-PHASE, MULTI-LEVEL ENCODING 审中-公开
公开(公告)号：WO2023038737A1
公开(公告)日：2023-03-16
申请号：PCT/US2022/039178
申请日：2022-08-02
申请人： QUALCOMM INCORPORATED
发明人： LEE, Chulkyu , LEE, Jeffrey Charles , WILEY, George Alan
IPC分类号： H04L7/00 , H04L7/033
摘要： An apparatus has a plurality of multi-level comparison circuits, each coupled to a pair of wires in a three-wire communication link, a plurality of first-level clock recovery circuits and a second-level clock recovery circuit. Each multi-level comparison circuit provides a multibit signal as an output. Each first-level clock recovery circuit includes a plurality of first-level flipflops clocked by transitions in a multibit signal received from one of the multi-level comparison circuits, and a first delay circuit that delays an output of the each first-level clock recovery circuit to provide a first reset signal that resets the each first-level clock recovery circuit. The second-level clock recovery circuit includes a second-level flipflop clocked by transitions in the outputs of the plurality of first-level clock recovery circuits, and a second delay circuit that delays an output of the second-level clock recovery circuit to provide a second reset signal to the second-level flipflop.

35. 发明申请

WO2022119714A1 CELL ARCHITECTURE WITH AN ADDITIONAL OXIDE DIFFUSION REGION 审中-公开
公开(公告)号：WO2022119714A1
公开(公告)日：2022-06-09
申请号：PCT/US2021/059697
申请日：2021-11-17
申请人： QUALCOMM INCORPORATED
发明人： CHINTARLAPALLI REDDY, Harikrishna , SANA, Pradeep Kumar , LEE, Chulkyu , LEE, Jeffrey Charles , MOHAMAD, Sajin
IPC分类号： H01L21/8238 , H01L27/02 , H01L27/092
摘要： A MOS device (300) includes a set of pMOS transistors (302) on a first side of an IC. The set of pMOS transistors is adjacent to each other in a second direction. The MOS device further includes a set of nMOS transistors (312) on a second side of the IC. The set of nMOS transistors is adjacent to each other in the second direction. The second side is opposite the first side in a first direction orthogonal to the second direction. The MOS device further includes an OD region (324) between the set of pMOS transistors and the set of nMOS transistors. A first set of gate interconnects (326) may extend in the first direction over the OD region. A set of contacts (328) may contact the OD region. The OD region, the first set of gate interconnects, and the set of contacts may form a set of transistors configured as dummy transistors or decoupling capacitors.

36. 发明申请

WO2021188724A1 TERMINATION FOR HIGH-FREQUENCY TRANSMISSION LINES 审中-公开
公开(公告)号：WO2021188724A1
公开(公告)日：2021-09-23
申请号：PCT/US2021/022833
申请日：2021-03-17
申请人： QUALCOMM INCORPORATED
发明人： LEE, Chulkyu , PARK, Hyunjeong
IPC分类号： G06F13/40 , H03H7/38 , H04B3/14 , H04L25/02 , H04L25/03
摘要： A termination for a high-frequency transmission line includes a first resistor (1214) that has a first terminal coupled to a first end of a transmission line (1210) and a second terminal coupled to a first input/output pad (1212), and a second resistor (1216) that has a first terminal coupled to the first input/output pad (1212). The first resistor (1214) and the second resistor (1216) may provide a combined resistance that matches a nominal value of a characteristic impedance of the transmission line (1210). The apparatus may include a third resistor having a first terminal coupled to a second end of a transmission line, and a second terminal coupled to a second input/output pad, and a fourth resistor having a first terminal coupled to the second input/output pad. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line.

37. 发明申请

WO2020068293A1 C-PHY RECEIVER EQUALIZATION 审中-公开
公开(公告)号：WO2020068293A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/046728
申请日：2019-08-16
申请人： QUALCOMM INCORPORATED
发明人： LEE, Chulkyu , SHIN, Jae Min , WILEY, George Alan
IPC分类号： H04L25/03 , H04L25/14 , H04L25/49
摘要： Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method includes equalizing three-phase signals received from two wires of the interface to provide equalized signals, providing first and second difference signals by comparing voltage differences between the equalized signals with first and second reference voltage levels respectively, capturing delayed and undelayed versions of the second difference signal using flipflops triggered by different edges in the first difference signal, and adjusting an equalizing circuit until outputs of the first flipflops indicate that a ratio of low-frequency attenuation to high-frequency amplification has been achieved that enables information to be accurately decoded from the three-phase signals. The three-phase signal received from a first of the two wires is in a different phase than the three-phase signal received from a second of the two wires.

38. 发明申请

WO2019045973A1 PROVIDING ZERO-OVERHEAD FRAME SYNCHRONIZATION USING SYNCHRONIZATION STROBE POLARITY FOR SOUNDWIRE EXTENSION BUSES 审中-公开
公开(公告)号：WO2019045973A1
公开(公告)日：2019-03-07
申请号：PCT/US2018/045739
申请日：2018-08-08
申请人： QUALCOMM INCORPORATED
发明人： AMARILIO, Lior , LEE, Chulkyu , RAJ, Harvijaysinh
IPC分类号： G06F3/16 , H04L7/00 , G11C7/10
摘要： Providing zero-overhead frame synchronization using synchronization strobe polarity for SOUNDWIRE Extension buses is disclosed. In one aspect, a downstream-facing interface (DFI) device determines a polarity of a next synchronization strobe of a bitstream based on a value of a next frame synchronization pattern, and adjusts the next synchronization strobe of the bitstream to comprise a signal transition corresponding to the polarity. The processor-based DFI device then transmits the bitstream containing the next synchronization strobe (e.g., via a SOUNDWIRE Extension bus, such as a SOUNDWIRE-XL or SOUNDWIRE-NEXT bus, to one or more upstream-facing interface (UFI) devices). In another aspect, a processor-based UFI device receives the bitstream, and detects the encoded polarity of the synchronization strobe. The processor-based UFI device reconstructs the frame synchronization pattern based on the polarity of the synchronization strobe, and performs frame synchronization based on the frame synchronization pattern.

39. 发明申请

WO2018226360A1 THREE-INPUT CONTINUOUS-TIME AMPLIFIER AND EQUALIZER FOR MULTI-LEVEL SIGNALING 审中-公开
公开(公告)号：WO2018226360A1
公开(公告)日：2018-12-13
申请号：PCT/US2018/032151
申请日：2018-05-10
申请人： QUALCOMM INCORPORATED
发明人： LEE, Chulkyu , CHOU, Shih-Wei , DUAN, Ying
IPC分类号： H03F3/21 , H03F3/45 , H04B1/06
摘要： A receiver amplifier and also a receiver equalizer is provided for a three-level signaling system. The receiver amplifier includes a single current source that drives a current into node shared by three transistors arranged in parallel. A trio of input signals corresponds to the three transistors on a one-to-one basis. Each input signal drives the gate of its corresponding transistor. In addition, each transistor produces a corresponding output voltage at a terminal coupled to a resistor. The receiver equalizer includes three transistors and three corresponding equalizing pairs of a resistor and a capacitor. A terminal for the capacitor and for the resistor in each equalizing pair connects to a terminal of the corresponding transistor.

40. 发明申请

WO2017180281A1 MULTI-WIRE SIGNALING WITH MATCHED PROPAGATION DELAY AMONG WIRE PAIRS 审中-公开
标题翻译：多线信号在线对中具有匹配传播延迟
公开(公告)号：WO2017180281A1
公开(公告)日：2017-10-19
申请号：PCT/US2017/022368
申请日：2017-03-14
申请人： QUALCOMM INCORPORATED
发明人： PANDEY, Shree Krishna , KUNDU, Arun Chandra , WILEY, George Alan , LEE, Chulkyu
IPC分类号： H04L25/02
CPC分类号： H04L25/0272 , H04B3/46 , H04L25/02 , H04L25/0292 , H04L25/0298
摘要： In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.
摘要翻译：在包括至少三根导线的多导线通道中，多导线通道的每对唯一导线对具有大致相同的信号传播时间。通过这种方式，可以在多线信道中缓解抖动，用于发送信号，其中对于给定的数据传输，差分信号在特定的一对导线上传输，并且每个其他导线都是浮动的。在一些实现中，信号传播时间的匹配涉及为至少一个导线提供附加延迟。使用无源信号延迟技术和/或有源信号延迟技术来提供附加延迟。

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