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31. 发明申请

WO2017052654A1 SCALED INTERCONNECT VIA AND TRANSISTOR CONTACT BY ADJUSTING SCATTERING 审中-公开
标题翻译：通过调整散射来连接通过和晶体管的连接
公开(公告)号：WO2017052654A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052483
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： AVCI, Uygar E. , YOUNG, Ian A.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L23/485 , H01L29/41791 , H01L29/785
摘要： Described is an apparatus which comprises: a via formed of a first material; and a first interconnect, formed of a second material, with an end region coupled to the via, wherein the first interconnect has an angled sidewall at the end region. Described is an apparatus which comprises: a via formed of a first material; and a first interconnect, formed of a second material, with an end region coupled to the via, wherein the first interconnect has a rougher interface for at least one wall of the first interconnect at the end region compared to at least another wall of the first interconnect.
摘要翻译：描述了一种装置，包括：由第一材料形成的通孔; 以及由第二材料形成的第一互连，其中端部区域耦合到所述通孔，其中所述第一互连件在所述端部区域具有成角度的侧壁。描述了一种装置，包括：由第一材料形成的通孔; 以及由第二材料形成的第一互连，其端部区域耦合到所述通孔，其中所述第一互连件具有用于所述端部区域处的所述第一互连件的至少一个壁的粗糙界面，与所述第一互连件的至少另一个壁相比较互连。

32. 发明申请

WO2017034564A1 SINGLE PULSE MAGNETO-STRICTIVE SWITCHING VIA HYBRID MAGNETIZATION STACK 审中-公开
标题翻译：通过混合磁化堆栈的单脉冲磁控开关
公开(公告)号：WO2017034564A1
公开(公告)日：2017-03-02
申请号：PCT/US2015/047056
申请日：2015-08-26
申请人： INTEL CORPORATION
发明人： NIKONOV, Dmitri E. , MANIPATRUNI, Sasikanth , CHAUDHRY, Anurag , YOUNG, Ian A.
IPC分类号： H01L43/08 , H01F10/08
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1673 , G11C11/1675
摘要： Described is an apparatus which comprises: a first ferromagnetic (FM) layer with magneto-strictive (MS) property; a layer operable to exert strain on the first FM layer; and a first anti-FM layer coupled to the layer and operable to exert exchange bias on the first FM layer.
摘要翻译：描述了一种装置，其包括：具有磁致伸缩（MS）特性的第一铁磁（FM）层; 可操作以在所述第一FM层上施加应变的层; 以及耦合到所述层并且可操作以在所述第一FM层上施加交换偏压的第一抗FM层。

33. 发明申请

WO2016094320A1 INTERCONNECT WAKE RESPONSE CIRCUIT AND METHOD 审中-公开
标题翻译：互连唤醒响应电路和方法
公开(公告)号：WO2016094320A1
公开(公告)日：2016-06-16
申请号：PCT/US2015/064326
申请日：2015-12-07
申请人： INTEL CORPORATION
发明人： SRIVASTAVA, Amit Kumar , LEE, Jia Jun , AZAM, Asad
IPC分类号： G06F1/32 , G06F13/42 , G06F13/38
CPC分类号： G06F1/3287 , G06F1/3215 , G06F1/3253 , G06F1/3278 , G06F1/3296 , G06F9/4418 , G06F13/4282 , Y02D10/151 , Y02D10/157
摘要： In some embodiments, provided are circuits and approaches for responding to wake requests over a data bus such as with a USB interface. An interconnect PHY may be placed into an aggressive power reduction mode and in response to a detected wake request on the bus, respond in a sufficient time by keeping at least a portion of a transmitter data path in the PHY powered on during the reduced power mode and responding to the wake request while the PHY re-boots in the background.
摘要翻译：在一些实施例中，提供了用于通过诸如USB接口的数据总线响应唤醒请求的电路和方法。互连PHY可以被放置在积极的功率降低模式中，并且响应于在总线上检测到的唤醒请求而响应，在足够的时间通过在减少的功率模式期间保持PHY中的发射机数据路径的至少一部分被上电并在PHY在后台重新启动时响应唤醒请求。

34. 发明申请

WO2016093994A1 METHOD AND APPARATUS FOR PASSIVE CONTINUOUS-TIME LINEAR EQUALIZATION WITH CONTINUOUS-TIME BASELINE WANDER CORRECTION 审中-公开
标题翻译：连续时间线性均衡的连续时间线性校正的方法和装置
公开(公告)号：WO2016093994A1
公开(公告)日：2016-06-16
申请号：PCT/US2015/059519
申请日：2015-11-06
申请人： INTEL CORPORATION
发明人： ISLAM, Syed S. , HO, Yick Yaw , SWARTZ, Ronald W.
IPC分类号： H04L25/03 , H03F3/45
CPC分类号： H04L25/03057 , H04L25/0272 , H04L25/0296 , H04L25/03254 , H04L25/03885 , H04L25/06 , H04L25/10
摘要： Described is an apparatus which comprises: an amplifier; and a passive continuous-time linear equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.
摘要翻译：描述了一种装置，包括：放大器; 以及与基线漂移（BLW）校正器集成的被动连续时间线性均衡器，其中集成均衡器和BLW校正器耦合到放大器。

35. 发明申请

WO2015094252A1 DIGITAL SYNTHESIZABLE LOW DROPOUT REGULATOR WITH ADAPTIVE GAIN 审中-公开
标题翻译：具有自适应增益的数字合成低压差型稳压器
公开(公告)号：WO2015094252A1
公开(公告)日：2015-06-25
申请号：PCT/US2013/076298
申请日：2013-12-18
申请人： INTEL CORPORATION
发明人： MUTHUKARUPPAN, Ramnarayanan , PATRA, Pradipta , GOEL, Gaurav , KADALI, Uday Bhaskar
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G05F1/59
摘要： Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
摘要翻译：描述了具有自适应增益的电压调节器，其包括：可由数字总线控制的多个功率门晶体管，所述多个功率栅极晶体管可操作以向负载提供第一电源，以及接收第二电源作为输入; 模数转换器（ADC），用于接收第一电源并产生代表第一电源的数字输出; 以及控制器，用于接收代表第一电源的数字输出并产生用于控制多个功率门晶体管的数字总线，使得多个功率门晶体管的传递函数在工作范围内基本上是线性的。

36. 发明申请

WO2015084335A1 APPARATUS AND METHOD FOR EXTENDING FREQUENCY RANGE OF A CIRCUIT AND FOR OVER-CLOCKING OR UNDER-CLOCKING 审中-公开
标题翻译：用于延长电路频率范围和超时钟或欠时钟的装置和方法
公开(公告)号：WO2015084335A1
公开(公告)日：2015-06-11
申请号：PCT/US2013/072924
申请日：2013-12-03
申请人： INTEL CORPORATION
发明人： MUSUNURI, Surya , RAPETA, Jagannadha R. , ELZINGA, Mark L. , PARK, Young Min , FULTON, Robert R.
IPC分类号： G06F1/08
CPC分类号： G06F1/08 , G06F13/36 , G06F13/4068 , H03L7/183 , H03L2207/50
摘要： Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.
摘要翻译：描述了一种用于超频或欠时钟的装置，该装置包括：具有反馈分频器的锁定环路（例如，锁相环或锁频环路），锁定环路接收参考时钟并将其与反馈分频器输出的反馈时钟，并产生输出时钟; 耦合到锁定环路的锁相环分路器，用于接收输出时钟并产生用于其它逻辑单元的基本时钟; 以及用于分别用于反馈分频器和锁相环分频器的第一和第二分频器比较器的控制逻辑，用于超频或欠时钟基本时钟，使得锁定环路在被超频或欠频的情况下保持锁定。

37. 发明申请

WO2015080738A1 CONTINUOUS CURRENT MODE MULTI-LOAD POWER REGULATOR 审中-公开
标题翻译：连续电流模式多负载功率调节器
公开(公告)号：WO2015080738A1
公开(公告)日：2015-06-04
申请号：PCT/US2013/072329
申请日：2013-11-27
申请人： INTEL CORPORATION
发明人： VAIDYA, Vaibhav , RAVICHANDRAN, Krishnan , COWLEY, Nicholas P.
IPC分类号： H02M7/00 , G05F1/40
CPC分类号： H02M1/088 , H02M3/07 , H02M3/158 , H02M2001/0087 , H02M2001/009
摘要： Described is an apparatus which comprises: an interconnect to provide current; a bridge having a high-side switch and a low-side switch, wherein the high-side switch and the low-side switch are coupled to an inductor, and wherein the inductor is coupled to the interconnect; a plurality of switching load stages coupled to the interconnect, wherein each of the switching load stages of the plurality to provide a voltage supply to a load; a first controller to control duty cycle of an input to the bridge to regulate the current provided to the interconnect; and a second controller to control duty cycle of a plurality of inputs, each input to be received by a corresponding switching load stage of the plurality of switching load stages.
摘要翻译：描述了一种装置，其包括：提供电流的互连; 具有高侧开关和低侧开关的桥，其中所述高侧开关和所述低侧开关耦合到电感器，并且其中所述电感器耦合到所述互连; 耦合到所述互连的多个开关负载级，其中所述多个开关负载级中的每一个为负载提供电压供应; 第一控制器，用于控制到桥的输入的占空比以调节提供给互连的电流; 以及第二控制器，用于控制多个输入的占空比，每个输入由所述多个开关负载级的对应的开关负载级接收。

38. 发明申请

WO2015076789A1 CLOCK CALIBRATION USING ASYNCHRONOUS DIGITAL SAMPLING 审中-公开
标题翻译：使用异步数字采样的时钟校准
公开(公告)号：WO2015076789A1
公开(公告)日：2015-05-28
申请号：PCT/US2013/070824
申请日：2013-11-19
申请人： INTEL CORPORATION
发明人： BALAMURUGAN, Ganesh , MANSURI, Mozhgan , HYVONEN, Sami , CASPER, Bryan, K. , O'MAHONY, Frank
IPC分类号： H03L7/00 , H04L7/00
CPC分类号： H03L7/00 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C7/222 , H03K5/1565 , H03L7/08 , H04B1/04 , H04L25/03
摘要： Described is an apparatus which comprises: an asynchronous clock generator to generate an asynchronous clock signal; a digital sampler for sampling a signal using the asynchronous clock signal; a duty cycle corrector (DCC) to receive a differential input clock and to generate a differential output clock, wherein the digital sampler to sample at least one of an output clock from the differential output clock; and a counter to count output of the digital sampler and to provide a control to the DCC to adjust duty cycle of the differential output clock.
摘要翻译：描述了一种装置，其包括：异步时钟发生器，用于产生异步时钟信号; 数字采样器，用于使用异步时钟信号对信号进行采样; 用于接收差分输入时钟并产生差分输出时钟的占空比校正器（DCC），其中所述数字采样器从所述差分输出时钟采样至少一个输出时钟; 以及计数器来计数数字采样器的输出，并向DCC提供控制以调整差分输出时钟的占空比。

39. 发明申请

WO2015065480A1 INVERTER-EMBEDDED SILICON CONTROLLED RECTIFIER 审中-公开
标题翻译：逆变器嵌入式硅控制整流器
公开(公告)号：WO2015065480A1
公开(公告)日：2015-05-07
申请号：PCT/US2013/068141
申请日：2013-11-01
申请人： INTEL CORPORATION , JACK, Nathan D. , POON, Steven S.
发明人： JACK, Nathan D. , POON, Steven S.
IPC分类号： H01L27/02
CPC分类号： H02H9/04 , G06F1/16 , H01F38/14 , H01L27/0262 , H01L29/66325 , H01L29/7436 , H02H9/046 , H02J5/005
摘要： Described is a low power clamp or driver comprising: an inverter; and a silicon controlled rectifier (SCR) embedded in the inverter such that the SCR is part of the inverter. The clamp offers improved conductance per area and lower leakage current compared to the traditional PMOS-based active rail clamps. The clamp or driver combines a trigger circuit with the inverter-embedded SCR for maximum area efficiency. The clamp or driver also result in less stringent requirements for power ramp rates.
摘要翻译：描述了一种低功率钳位或驱动器，包括：逆变器; 以及嵌入在逆变器中的可控硅整流器（SCR），使得SCR是逆变器的一部分。与传统的基于PMOS的主动轨道夹具相比，钳位提供了每面积更高的电导和更低的漏电流。钳位或驱动器将触发电路与逆变器嵌入式SCR组合，实现最大的面积效率。钳位或驱动器也对功率斜坡率有较不严格的要求。

40. 发明申请

WO2015047337A1 APPARATUS AND METHOD TO OPTIMIZE STT-MRAM SIZE AND WRITE ERROR RATE 审中-公开
标题翻译：优化STT-MRAM尺寸和写错误率的装置和方法
公开(公告)号：WO2015047337A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/062421
申请日：2013-09-27
申请人： INTEL CORPORATION
发明人： MANIPATRUNI, Sasikanth , NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： G11C11/15
CPC分类号： G11C13/0069 , G11C7/12 , G11C11/16 , G11C11/1653 , G11C11/1655 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/5607 , G11C2213/79 , G11C2213/82
摘要： Described is an apparatus comprising: a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. Described is a magnetic random access memory (MRAM) comprising: a plurality of rows, each row including: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; and a plurality of buffers, each of which to buffer a select-line signal for a group of bit-cells among the plurality of bit-cells; and a plurality of bit-lines, each row sharing a single bit-line among the plurality of bit-cells in that row.
摘要翻译：描述了一种装置，包括：第一选择线; 第二选择线; 有点线第一位单元，包括电阻存储元件和晶体管，所述第一位单元耦合到所述第一选择线和所述位线; 具有耦合到第一选择线的输入和耦合到第二选择线的输出的缓冲器; 以及包括电阻存储元件和晶体管的第二位单元，所述第二位单元耦合到所述第二选择线和所述位线。描述了一种磁性随机存取存储器（MRAM），包括：多行，每行包括：多个位单元，每个位单元具有耦合到晶体管的MTJ器件; 以及多个缓冲器，每个缓冲器用于缓冲所述多个位单元中的一组位单元的选择线信号; 和多个位线，每行在该行中的多个位单元之中共享单个位线。

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