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31. 发明申请

WO2020074934A1 IMPROVED VEHICLE COMMUNICATION 审中-公开
公开(公告)号：WO2020074934A1
公开(公告)日：2020-04-16
申请号：PCT/IB2018/001166
申请日：2018-10-12
申请人： MICRON TECHNOLOGY , INC.
发明人： TROIA, Alberto , MONDELLO, Antonino
IPC分类号： G07C9/00
摘要： The present disclosure relates to an apparatus comprising a processor unit and an external communication component coupled to the processor unit. The external communication component, in response to determining that an approaching entity is within a particular proximity thereof, is configured to generate an external private key and an external public key, provide the external public key to a communication component associated with the approaching entity, receive data from the communication component of the approaching entity in response to providing the external public key to the communication component associated with that approaching entity, decrypt the received data using the external private key, and authorize the transit of the approaching entity through a limited access gate based on the decrypted received data. An approaching entity apparatus and related communication methods are also described.

32. 发明申请

WO2020074933A1 METHOD AND APPARATUS TO RECOGNIZE TRANSPORTED PASSENGERS AND GOODS 审中-公开
公开(公告)号：WO2020074933A1
公开(公告)日：2020-04-16
申请号：PCT/IB2018/001165
申请日：2018-10-12
申请人： MICRON TECHNOLOGY, INC.
发明人： TROIA, Alberto , MONDELLO, Antonio
IPC分类号： B60R25/102 , B60W40/08 , G07C5/00
摘要： It is disclosed an apparatus comprising: a vehicle computing device (110) including a processor (120); an internal wireless communication component (130) associated to the vehicle computing device (110) and coupled to the processor (120); a memory portion (160) associated to said processor unit and structured to store information and data relating at least to passengers, luggage or goods on the vehicle; said information and data being automatically transmitted to said vehicle computing device and to said memory through said internal wireless communication component.

33. 发明申请

WO2015153255A1 APPARATUSES AND METHODS FOR COMPARING DATA PATTERNS IN MEMORY 审中-公开
标题翻译：用于比较记忆中数据模式的装置和方法
公开(公告)号：WO2015153255A1
公开(公告)日：2015-10-08
申请号：PCT/US2015/022636
申请日：2015-03-26
申请人： MICRON TECHNOLOGY, INC.
发明人： MANNING, Troy, A.
IPC分类号： G11C7/10 , G11C7/06
CPC分类号： G11C15/043 , G11C7/1006 , G11C11/4091
摘要： The present disclosure includes apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array via an input/output (I/O) line.
摘要翻译：本公开包括与比较存储器中的数据模式相关的装置和方法。示例性方法可以包括将存储在存储器阵列中的多个数据模式与目标数据模式进行比较。该方法可以包括确定数据模式数量的数据模式是否与目标数据模式匹配，而不经由输入/输出（I / O）线路从存储器阵列传送数据。

34. 发明申请

WO2012060858A1 DATA SIGNAL MIRRORING 审中-公开
标题翻译：数据信号镜像
公开(公告)号：WO2012060858A1
公开(公告)日：2012-05-10
申请号：PCT/US2011/001800
申请日：2011-10-24
申请人： MICRON TECHNOLOGY, INC. , ABRAHAM, Michael, M. , FEELEY, Peter
发明人： ABRAHAM, Michael, M. , FEELEY, Peter
IPC分类号： G11C7/10 , G11C16/06 , G06F12/16 , G06F13/14
CPC分类号： G06F17/30575 , G06F12/16 , G06F13/1694 , G11C7/1006
摘要： Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data inputs/outputs of a memory component, and responsive to determining that a mirrored version of the particular data pattern is received by the memory component, configuring the number of data inputs/outputs to be mirrored.
摘要翻译：描述了用于数据信号镜像的方法，设备和系统。一种或多种方法包括在存储器组件的多个数据输入/输出上接收特定数据模式，并且响应于确定特定数据模式的镜像版本被存储器组件接收，配置数据输入/ 输出要镜像。

35. 发明申请

WO2012026962A2 PHASE CHANGE MEMORY STRUCTURES AND METHODS 审中-公开
标题翻译：相变存储器结构和方法
公开(公告)号：WO2012026962A2
公开(公告)日：2012-03-01
申请号：PCT/US2011/001437
申请日：2011-08-17
申请人： MICRON TECHNOLOGY, INC. , LIU, Jun
发明人： LIU, Jun
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L45/126 , G11C13/0004 , H01L45/06 , H01L45/144 , H01L45/16
摘要： Methods, devices, and systems associated with phase change memory structures are described herein. One method of forming a phase change memory structure includes forming an insulator material on a first conductive element and on a dielectric material of a phase change memory cell, forming a heater self-aligned with the first conductive element, forming a phase change material on the heater and at least a portion of the insulator material formed on the dielectric material, and forming a second conductive element of the phase change memory cell on the phase change material.
摘要翻译：这里描述了与相变存储器结构相关联的方法，设备和系统。形成相变存储器结构的一种方法包括在第一导电元件上和相变存储单元的介电材料上形成绝缘体材料，形成与第一导电元件自对准的加热器，在第一导电元件上形成相变材料加热器和在介电材料上形成的至少一部分绝缘体材料，并且在相变材料上形成相变存储单元的第二导电元件。

36. 发明申请

WO2011142799A2 DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS 审中-公开
标题翻译：在存储器件和系统中确定和使用软数据
公开(公告)号：WO2011142799A2
公开(公告)日：2011-11-17
申请号：PCT/US2011/000761
申请日：2011-05-02
申请人： MICRON TECHNOLOGY, INC. , RADKE, William, H. , SHEN, Zhenlei , FEELEY, Peter
发明人： RADKE, William, H. , SHEN, Zhenlei , FEELEY, Peter
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C16/26 , G11C7/14 , G11C11/26 , G11C11/5628 , G11C11/5642 , G11C16/349 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/50004
摘要： The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.
摘要翻译：本公开包括用于在存储器设备和系统中确定和使用软数据的方法，设备和系统。一个或多个实施例包括耦合到阵列的存储器单元阵列和控制电路。控制电路被配置为使用多个感测电压对存储器单元执行多个感测操作，以确定与存储器单元的目标状态相关联的软数据，并且基于以下方式调整用于确定目标状态的感测电压：最少部分地在确定的软数据上。

37. 发明申请

WO2011129874A3 BOOT PARTITIONS IN MEMORY DEVICES AND SYSTEMS 审中-公开
公开(公告)号：WO2011129874A3
公开(公告)日：2011-10-20
申请号：PCT/US2011/000651
申请日：2011-04-11
申请人： MICRON TECHNOLOGY, INC. , GALBO, Neal, A. , TSAI, Victor, Y. , RADKE, William, H. , DATLA, Krishnam, R.
发明人： GALBO, Neal, A. , TSAI, Victor, Y. , RADKE, William, H. , DATLA, Krishnam, R.
IPC分类号： G06F12/02
摘要： The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition.

38. 发明申请

WO2011093995A2 GCIB-TREATED RESISTIVE DEVICE 审中-公开
标题翻译： GCIB处理电阻器件
公开(公告)号：WO2011093995A2
公开(公告)日：2011-08-04
申请号：PCT/US2011/000134
申请日：2011-01-25
申请人： MICRON TECHNOLOGY, INC. , SMYTHE III, John, A. , SANDHU, Gurtej, S.
发明人： SMYTHE III, John, A. , SANDHU, Gurtej, S.
IPC分类号： H01L27/105 , H01L21/8247
CPC分类号： H01L45/165 , G11C13/0007 , G11C2213/56 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1641 , H01L45/1683
摘要： The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.
摘要翻译：本公开包括GCIB处理的电阻性装置，利用GCIB处理的电阻性装置（例如，作为开关，存储器单元）的装置以及用于形成经GCIB处理的电阻装置的方法。形成GCIB处理的电阻性器件的一种方法包括形成下电极，并在下电极上形成氧化物材料。将氧化物材料暴露于气体簇离子束（GCIB），直到氧化物材料的第一部分的电阻相对于氧化物材料的第二部分的电阻发生变化。在第一部分上形成上电极。

39. 发明申请

WO2011040950A2 POWER INTERRUPT MANAGEMENT 审中-公开
标题翻译：电力中断管理
公开(公告)号：WO2011040950A2
公开(公告)日：2011-04-07
申请号：PCT/US2010/002557
申请日：2010-09-20
申请人： MICRON TECHNOLOGY, INC. , JEDDELOH, Joseph, M.
发明人： JEDDELOH, Joseph, M.
IPC分类号： G06F12/02 , G06F9/44 , G06F13/10
CPC分类号： G06F1/30 , G06F11/141 , G06F11/1441 , G06F12/0215 , G06F12/0246 , G06F2212/1032 , G06F2212/214 , G06F2212/7201 , G06F2212/7207 , G06F2212/7209 , G06F2212/7211
摘要： The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log.
摘要翻译：本公开包括用于操作存储器系统和存储器系统的方法。一种这样的方法包括使用写入预览信息来更新事务日志中的事务日志信息; 以及使用事务日志更新逻辑地址（LA）表。

40. 发明申请

WO2011031302A3 MEMORY KINK CHECKING 审中-公开
公开(公告)号：WO2011031302A3
公开(公告)日：2011-03-17
申请号：PCT/US2010/002378
申请日：2010-08-31
申请人： MICRON TECHNOLOGY, INC. , CHANDRASEKHAR, Uday , HELM, Mark
发明人： CHANDRASEKHAR, Uday , HELM, Mark
IPC分类号： G11C16/10
摘要： This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
摘要翻译：本公开涉及存储器扭结检查。一个实施例包括根据第一存储器单元的编程状态将多个电压中的一个选择性地施加到第一数据线，其中第一存储器单元耦合到第一数据线并耦合到选定的存取线。至少部分由于施加到第一数据线的电压以及至少第一数据线和第二数据线之间的电容耦合而确定对第二数据线的影响，其中第二数据线耦合到第第二存储器单元，第二存储器单元与第一存储器单元相邻，并且第二存储器单元耦合到选择的存取线。在施加到第二存储器单元的后续编程脉冲期间，扭曲校正响应于所确定的效果被施加到第二数据线。

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