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21. 发明申请

WO00035087A1 REAL-TIME TECHNIQUE FOR REDUCING THE SETTLING TIME OF A HIGH PASS FILTER 审中-公开
标题翻译：实时技术降低高通滤波器的设定时间
公开(公告)号：WO00035087A1
公开(公告)日：2000-06-15
申请号：PCT/US1999/027707
申请日：1999-11-22
IPC分类号： A61B5/022 , H03H17/02
CPC分类号： H03H17/0219
摘要： A technique for resetting an HPF for improving its settling time in response to a sharp transition in its input signal, by rapid input and clocking through the HPF of new data samples after occurrence of the sharp transition. The new data samples comprise an artifical ramp representative of the expected average slope of the input signal that should be maintained after occurence of the sharp transition. The artificial ramp can be generated using "a priori" knowledge of the expected average slope of the input signal, or alternatively, can be generated using a direct measurement of the slope of the input signal at the time the HPF is to be reset. In the event that both the direct slope measurement and "a priori" slope knowledge are available at the time the HPF is to be reset, and they differ from each other, it is desirable to generate an artificial ramp whose slope provides a smoothed transition from the latter slope measurement to the former slope.
摘要翻译：一种技术，用于通过快速输入和通过快速转换发生后的新数据样本的HPF来重新设置HPF，以改善其建立时间，以响应其输入信号的急剧转变。新的数据样本包括代表在发生急剧转变之后应该保持的输入信号的预期平均斜率的人造斜坡。可以使用对输入信号的预期平均斜率的“先验”知识来生成人造斜坡，或者可以使用在HPF被复位时直接测量输入信号的斜率来生成。在HPF要复位时，直接斜率测量和“先验”斜率知识都可用，并且它们彼此不同的情况下，希望产生一个人造斜坡，其斜坡提供平滑的过渡后者斜率测量到前一坡。

22. 发明申请

WO9939440A3 DEVICE FOR PROCESSING A DIGITAL SIGNAL 审中-公开
标题翻译：处理数字信号的装置
公开(公告)号：WO9939440A3
公开(公告)日：1999-09-23
申请号：PCT/IB9900092
申请日：1999-01-21
申请人： KONINKL PHILIPS ELECTRONICS NV , PHILIPS SVENSKA AB
发明人： NUIJTEN PETRUS A C M
IPC分类号： H03M1/66 , H03H17/02 , H03M1/12 , H03M3/02 , H03M7/36 , H03H17/04
CPC分类号： H03M7/3042 , H03H17/0219 , H03M7/3026
摘要： The device for processing a digital signal comprises an input (10) for receiving the digital signal and an output (18) for supplying an output signal. The device further comprises filter means (14) coupled to the output (18) for deriving an error signal and adding means (12) coupled to the input (10) for supplying to the output (18) a sum of the digital signal and the error signal. The adding means (12) are embodied so as to supply the most significant symbols of the sum signal to the output (18) and to supply the least significant symbols of the sum signal to the filter means (14).
摘要翻译：用于处理数字信号的设备包括用于接收数字信号的输入端（10）和用于提供输出信号的输出端（18）。该装置还包括耦合到输出端（18）用于导出误差信号的滤波器装置（14）和耦合到输入端（10）的加法装置（12），用于向输出端（18）提供数字信号和错误信号。加法装置（12）被实施为将总和信号的最高有效符号提供给输出端（18）并且将和信号的最低有效符号提供给滤波器装置（14）。

23. 发明申请

WO2017180172A1 MAGNITUDE COMPENSATION TECHNIQUE FOR PROCESSING SINGLE-BIT WIDE DATA 审中-公开
标题翻译：单位宽数据处理的幅度补偿技术
公开(公告)号：WO2017180172A1
公开(公告)日：2017-10-19
申请号：PCT/US2016/038545
申请日：2016-06-21
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , HESTER, Dylan, Alexander
发明人： HESTER, Dylan, Alexander
IPC分类号： H03H17/02 , H03H17/06 , H03M1/66
CPC分类号： H03M1/0626 , H03H17/0219 , H03M1/66
摘要： Droop caused by a filter may be compensated by applying a pre-filter to the audio signal that cancels out, at least in part, the droop caused by the filter. The pre-filter may implement magnitude compensation that causes an approximately flat passband response when the pre-filtered signal is passed through the filter. The pre-filter may be applied to one-bit wide data streams, such as high-fidelity direct stream digital (DSD) audio data or other one-bit wide data such as pulse-density modulation (PDM) encoded data. The pre-filtering and filtering may be implemented in components of an audio processor, such as in a digital-to-analog converter (DAC). The pre-filtering may include upsampling the one-bit wide data to form symbols and substituting an eighth bit of the symbol with an inverted version of an earlier-received bit.
摘要翻译：由滤波器引起的下垂可以通过对音频信号应用预滤波器来补偿，所述预滤波器至少部分抵消由滤波器引起的下垂。预滤波器可以实施幅度补偿，当预滤波信号通过滤波器时，该幅度补偿导致近似平坦的通带响应。预滤波器可以应用于诸如高保真直接流数字（DSD）音频数据的一位宽数据流或诸如脉冲密度调制（PDM）编码数据的其他一位宽数据。预滤波和滤波可以在音频处理器的组件中实现，例如在数模转换器（DAC）中。预滤波可以包括对一位宽数据进行上采样以形成符号，并用先前接收的比特的反转版本替换符号的第八位。

24. 发明申请

WO2015110582A1 VERFAHREN ZUR ENTZERRUNG VON VERZERRTEN SIGNALEN UND EIN ZUGEHÖRIGES ENTZERRUNGSFILTER 审中-公开
标题翻译：法的信号进行均衡和失真相关联的均衡滤波器
公开(公告)号：WO2015110582A1
公开(公告)日：2015-07-30
申请号：PCT/EP2015/051366
申请日：2015-01-23
申请人： ROHDE & SCHWARZ GMBH & CO. KG
发明人： KUHWALD, Thomas , NITSCH, Bernhard
IPC分类号： H03M1/06 , G01R35/00 , H03M1/12
CPC分类号： H03H17/0213 , G01R35/005 , G06F17/14 , H03H17/0219 , H03M1/0626 , H03M1/1205 , H03M1/1215 , H03M1/1225 , H03M1/123
摘要： Das Entzerrungsfilter (12) führt eine Entzerrung von mindestens einem von einem Messaufbau (1) verzerrten Signal durch. Die Filterkoeffizienten des Entzerrungsfilters (12) lassen sich durch Minimierung einer Kostenfunktion K ermitteln, in der nur Sequenzen von Filterkoeffizienten berücksichtigt werden, die einen signifikanten Einfluss auf die Entzerrung ausüben.
摘要翻译：所述均衡滤波器（12）执行的测量结构（1）的失真信号中的至少一个的均衡。所述均衡滤波器（12）的滤波器系数可被确定K，其中仅滤波器系数的序列被考虑，其具有通过最小化成本函数的均衡一个显著影响。

25. 发明申请

WO2013110173A1 INFINITE IMPULSE RESPONSE FILTER ARCHITECTURE WITH IDLE-TONE REDUCTION 审中-公开
标题翻译：无限风险反应滤波器结构，具有空调减少
公开(公告)号：WO2013110173A1
公开(公告)日：2013-08-01
申请号：PCT/CA2013/000056
申请日：2013-01-22
申请人： MICROSEMI SEMICONDUCTOR ULC
发明人： JIN, Qu Gary
IPC分类号： H03H17/02 , H03M3/02
CPC分类号： G06F17/10 , H03H17/0219 , H03H17/04
摘要： A digital infinite impulse response filter has a plurality of cascaded filter elements, with each filter element defining a pole of the filter and wherein the poles lie inside a unit circle. The filter elements are configured such that the output of the last filter element is a real number. In one embodiment the poles are arranged as complex conjugate pairs. In another embodiment the real part of the output of each filter element is extracted before being passed to the next filter element. This architecture offers improved idle tone with reduced complexity.
摘要翻译：数字无限脉冲响应滤波器具有多个级联的滤波器元件，每个滤波器元件限定滤波器的极点，并且其中极点位于单位圆内。滤波器元件被配置为使得最后一个滤波器元件的输出是实数。在一个实施例中，极被布置为复共轭对。在另一个实施例中，每个滤波器元件的输出的实部在被传递到下一个滤波器元件之前被提取。这种架构提供了改进的空闲音调，降低了复杂性。

26. 发明申请

WO2012118483A1 CASCADED DIGITAL FILTERS WITH REDUCED LATENCY 审中-公开
标题翻译：缩减数字滤波器
公开(公告)号：WO2012118483A1
公开(公告)日：2012-09-07
申请号：PCT/US2011/026555
申请日：2011-02-28
申请人： AGILENT TECHNOLOGIES, INC. , ABRAMOVITCH, Daniel, Y. , MOON, Christopher, R.
发明人： ABRAMOVITCH, Daniel, Y. , MOON, Christopher, R.
IPC分类号： H03H17/02
CPC分类号： H03H17/0219 , H03H17/0223 , H03H17/0294 , H03H17/04 , H03H2017/022 , H03H2220/02
摘要： A filter and method for filtering a signal are disclosed. The filter is equivalent to a plurality of bi-quad filters connected in series, and is implemented on a digital processor that receives a sequence of signal values at a sampling rate characterized by a sampling interval and generates a filtered signal value upon receiving each received signal value. The filter has a latency that is less than the sampling interval. The filtered values can be generated by adding a term to a received signal value and multiplying the sum by a gain constant that depends on the filter constants. The added term does not depend on the current received signal value. The filter can be implemented in fixed-point integer arithmetic.
摘要翻译：公开了一种用于滤波信号的滤波器和方法。滤波器等效于串联连接的多个双二极管滤波器，并且在数字处理器上实现，该数字处理器以采样间隔为特征的采样率接收信号值序列，并且在接收到每个接收信号时产生滤波后的信号值值。该过滤器的延迟小于采样间隔。可以通过将一个项添加到接收到的信号值并将和乘以取决于滤波器常数的增益常数来生成滤波值。附加项不依赖于当前接收的信号值。滤波器可以用定点整数运算来实现。

27. 发明申请

WO2011085947A1 SAMPLING RATE CONVERTER DATA FLOW CONTROL MECHANISM 审中-公开
标题翻译：采样率转换器数据流量控制机制
公开(公告)号：WO2011085947A1
公开(公告)日：2011-07-21
申请号：PCT/EP2011/000034
申请日：2011-01-07
申请人： ST-ERICSSON SA , TUDOSE, Andrei
发明人： TUDOSE, Andrei
IPC分类号： H03H17/06 , H04L7/00
CPC分类号： H04L7/0029 , H03H17/0219 , H03H17/0621 , H03H17/0657
摘要： Sampling rate converter for performing a rate conversion of an incoming stream of data, clocked at a first frequency, and output at a second frequency; said converter comprising: a circuit (2) for up-sampling the incoming data stream; a filter (3) for filtering the up-sampled incoming data stream; an interpolation filter (4) for interpolating the filtered up-sampled incoming stream of data; a FIFO (5) for storing the interpolated filtered up-sampled incoming stream of data, said storing being performed at said first frequency and the reading of said FIFO being performed at said second frequency so as to output the stored data at a second corresponding rate; characterized in that it further comprises: a control block (10) comprising a numerically controlled oscillator (NCO) used for generating said first frequency, the control of said NCO being based on information representative of the status of said FIFO (5) and also information representative of the modulation of the data and ratio of sampling rate change.
摘要翻译：采样率转换器，用于执行以第一频率计时并以第二频率输出的输入数据流的速率转换; 所述转换器包括：用于对输入数据流进行上采样的电路（2）; 滤波器（3），用于过滤上采样的输入数据流; 内插滤波器（4），用于内插经滤波的上采样的数据流; 一个FIFO（5），用于存储内插滤波的上采样输入数据流，所述存储以所述第一频率执行，并且所述FIFO的读取以所述第二频率执行，以便以第二对应速率输出所存储的数据 ; 其特征在于，还包括：包括用于产生所述第一频率的数控振荡器（NCO）的控制块（10），所述NCO的控制是基于表示所述FIFO（5）的状态的信息，以及信息代表数据的调制和采样率的变化率。

28. 发明申请

WO2003023961A1 音質調整装置及びこれに用いるフィルタ装置、音質調整方法、フィルタの設計方法审中-公开
标题翻译：声音质量调节装置及其使用的滤波器，声音质量调节方法和滤波器设计方法
公开(公告)号：WO2003023961A1
公开(公告)日：2003-03-20
申请号：PCT/JP2002/009047
申请日：2002-09-05
申请人：酒井康江 , 小柳裕喜生
发明人：小柳裕喜生
IPC分类号： H03H17/06
CPC分类号： H03G3/002 , H03H17/0219 , H03H17/06
摘要： A filter circuit is composed of FIR filters, and the filter factor is of a symmetrical type, thereby realizing a linear phase characteristic and preventing phase distortion even if a desired frequency band is emphasized. The first filter factors of a low-pass filter are determined so that the first filter factors may be the terms of a sequence in which the sum of the terms is not zero, the sign of the sum of every other terms is the same as that of the other every other terms, and the sum of the every other terms is equal to that of the other every other terms. Thus, by only changing a part of the signs of the filter factors, second filter factors of a high-pass filter can be simply determined so that they may be the terms of a sequence in which the sum of the terms is zero, the sign of the sum of every other terms is opposite to that of the other every other terms, and the absolute value of the sum of the every other terms is equal to that of the other every other terms.
摘要翻译：滤波器电路由FIR滤波器构成，滤波器因子是对称型，从而实现线性相位特性，并且即使强调期望的频带也能防止相位失真。确定低通滤波器的第一滤波器因子，使得第一滤波器因子可以是术语的和不为零的序列的项，每个其他项的和的符号与的其他条款，其他条款的总和等于其他条款的总和。因此，通过仅改变滤波器因子的一部分符号，可以简单地确定高通滤波器的第二滤波器因子，使得它们可以是项的和为零的序列的项，符号每个其他条款的总和与其他条款的总和相反，每个其他条款的总和的绝对值等于其他每个条款的总和的绝对值。

29. 发明申请

WO1997009780A1 IMPROVED DIGITAL FILTER 审中-公开
标题翻译：改进的数字滤波器
公开(公告)号：WO1997009780A1
公开(公告)日：1997-03-13
申请号：PCT/IB1996000881
申请日：1996-09-02
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , PELGROM, Marcellinus, Johannes, Maria , MENTEN, Stefan, Eugene, Josephus
IPC分类号： H03H17/00
CPC分类号： H03H17/0219 , H03H17/023 , H03H17/06 , H03H2017/0232
摘要： In a digital filter in which coefficients are realised using power of two weighting factors, it can occur that due to rounding errors the output signal shows some inaccuracies. By decomposing the filter coefficients into powers of two in such a way that the most powers of two have a couterpart with an opposite sign, the rounding errors tend to cancel, resulting in a more accurate filter.
摘要翻译：在使用两个加权因子的功率实现系数的数字滤波器中，可能发生由于舍入误差导致的输出信号显示一些不准确。通过将滤波器系数分解为2的幂，使得两者的最大功率具有具有相反符号的couterpart，舍入误差倾向于消除，导致更准确的滤波器。

30. 发明申请

WO1980000393A1 APPARATUS FOR AND METHODS OF DIGITAL PROCESSING 审中-公开
标题翻译：数字处理的方法和方法
公开(公告)号：WO1980000393A1
公开(公告)日：1980-03-06
申请号：PCT/GB1979000129
申请日：1979-08-02
申请人： UNIVERSITY OF SURREY , MATLEY W , WILLIAMSON S , BYWATER R
发明人： UNIVERSITY OF SURREY
IPC分类号： H03H17/02
CPC分类号： H03H17/026 , H03H17/0219
摘要： A digital filter that removes from a digitised analogue signal those frequency components that would give rise to aliasing in a subsequent digital filtering operation, and does so without phase distortion. In a first stage (S1) of the filter successive overlapping groups of digitised sampled values are averaged, using a random access memory (2), an adder unit (3) and a parallel shift register (9). In a second stage (S2) successive non-overlapping groups of the averaged sampled values are accumulated (12) and averaged in a further parallel shift register (13). The second stage output may be converted to an analogue signal or supplied to a main digital filter (MDF), and the filter is particularly suited to microprocessor applications.
摘要翻译：数字滤波器，从数字化模拟信号中去除那些会在随后的数字滤波操作中产生混叠的频率分量，并且没有相位失真。在滤波器的第一级（S1）中，使用随机存取存储器（2），加法器单元（3）和并行移位寄存器（9）对数字化采样值的连续重叠组进行平均。在第二级（S2）中，平均采样值的连续非重叠组被累加（12）并在另一个并行移位寄存器（13）中进行平均。第二级输出可以转换为模拟信号或提供给主数字滤波器（MDF），并且滤波器特别适用于微处理器应用。

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