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21. 发明申请

WO2010060084A2 SYSTEMS, METHODS, AND APPARATUSES TO DECOMPOSE A SEQUENTIAL PROGRAM INTO MULTIPLE THREADS, EXECUTE SAID THREADS, AND RECONSTRUCT THE SEQUENTIAL EXECUTION 审中-公开
标题翻译：将连续程序分解为多个线程，执行线程并重新构建连续执行的系统，方法和设备
公开(公告)号：WO2010060084A2
公开(公告)日：2010-05-27
申请号：PCT/US2009065735
申请日：2009-11-24
申请人： INTEL CORP , LATORRE FERNANDO , CODINA JOSEP M , GIBERT ENRIC , LOPEZ PEDRO , MADRILES CARLOS , MARTINEZ ALEJANDRO , MARTINEZ RAUL , GONZALEZ ANTONIO
发明人： LATORRE FERNANDO , CODINA JOSEP M , GIBERT ENRIC , LOPEZ PEDRO , MADRILES CARLOS , MARTINEZ ALEJANDRO , MARTINEZ RAUL , GONZALEZ ANTONIO
IPC分类号： G06F9/30 , G06F12/00 , G06F13/00
CPC分类号： G06F9/3842 , G06F8/433 , G06F8/452 , G06F8/457 , G06F9/3851 , G06F9/3861
摘要： Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.
摘要翻译：描述了用于将顺序程序分解成多个线程，执行这些线程以及重建线程的顺序执行的系统，方法和装置。多个数据高速缓存单元（DCU）存储推测执行的线程的本地退役指令。合并级别缓存（MLC）合并来自DCU的行的数据。核心间存储器一致性模块（ICMC）全局退避MLC中推测执行的线程的指令。

22. 发明申请

WO2008136974A1 UNIVERSAL BRANCH IDENTIFIER FOR INVALIDATION OF SPECULATIVE INSTRUCTIONS 审中-公开
标题翻译：通用分支机构识别不定式说明书
公开(公告)号：WO2008136974A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/005509
申请日：2008-04-29
申请人： RMI CORPORATION , SINGH, Gaurav , SRINIVASAN, Srivatsan , RAMIREZ, Ricardo , CHEN, Wei-Hsiang , NGUYEN, Hai Ngoc
发明人： SINGH, Gaurav , SRINIVASAN, Srivatsan , RAMIREZ, Ricardo , CHEN, Wei-Hsiang , NGUYEN, Hai Ngoc
IPC分类号： G06F7/38
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path.
摘要翻译：投机分支预测系统。该系统的实施例包括分支预测逻辑，提取逻辑和分支识别逻辑。分支预测逻辑被配置为预测指令流中的分支的分支路径。提取逻辑耦合到分支预测逻辑。提取逻辑被配置为推测性地获取与预测的分支路径相对应的指令。分支识别逻辑耦合到分支预测逻辑和提取逻辑。分支识别逻辑被配置为使用通用分支标识格式使用分支标识符标记所推测的获取的指令。通用分支识别格式包括与预测分支路径相对应的比特位置处的比特值。

23. 发明申请

WO2008003019A3 METHODS AND APPARATUS FOR PROACTIVE BRANCH TARGET ADDRESS CACHE MANAGEMENT 审中-公开
标题翻译：主动分支目标地址高速缓存管理的方法和设备
公开(公告)号：WO2008003019A3
公开(公告)日：2008-05-02
申请号：PCT/US2007072317
申请日：2007-06-28
申请人： QUALCOMM INC , RYCHLIK BOHUSLAV
发明人： RYCHLIK BOHUSLAV
IPC分类号： G06F9/38
CPC分类号： G06F9/3848 , G06F9/3806 , G06F9/3844 , G06F9/3861
摘要： A multiple stage branch prediction system including a branch target address cache (BTAC) and a branch predictor circuit is disclosed. The BTAC is configured to store a BTAC entry. The branch predictor circuit is configured to store state information. The branch predictor circuit utilizes the state information to predict the direction of a branch instruction and to manage the BTAC entry based on the stored state information in response to actual resolution of the branch instruction.
摘要翻译：公开了一种包括分支目标地址高速缓存（BTAC）和分支预测电路的多级分支预测系统。 BTAC配置为存储BTAC条目。分支预测器电路被配置为存储状态信息。分支预测器电路利用状态信息来预测分支指令的方向，并且响应于分支指令的实际分辨率，基于存储的状态信息来管理BTAC条目。

24. 发明申请

WO2008039947A1 METHODS AND SYSTEM FOR RESOLVING SIMULTANEOUS PREDICTED BRANCH INSTRUCTIONS 审中-公开
标题翻译：解决同时预测分支指令的方法和系统
公开(公告)号：WO2008039947A1
公开(公告)日：2008-04-03
申请号：PCT/US2007/079781
申请日：2007-09-27
申请人： QUALCOMM Incorporated , SMITH, Rodney Wayne , STEMPEL, Brian Micheal , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
发明人： SMITH, Rodney Wayne , STEMPEL, Brian Micheal , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/30058 , G06F9/3844 , G06F9/3861
摘要： A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.
摘要翻译：公开了一种在预测分支指令验证之前解决同步分支预测的方法。该方法包括处理两个或多个预测分支指令，每个预测分支指令具有预测状态和校正状态。该方法还包括选择一个校正状态。如果预测的分支指令之一被错误预测，则所选择的校正状态用于指导未来的指令提取。

25. 发明申请

WO2007118769A1 AN ISSUE UNIT FOR PLACING A PROCESSOR INTO A GRADUAL SLOW MODE OF OPERATION 审中-公开
标题翻译：将处理者置于较慢的操作模式的问题单元
公开(公告)号：WO2007118769A1
公开(公告)日：2007-10-25
申请号：PCT/EP2007/052903
申请日：2007-03-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , ABERNATHY, Christopher, Michael , FEISTE, Kurt, Alan , VAN NORSTRAND, Albert, James, Jr. , HALL, Ronald
发明人： ABERNATHY, Christopher, Michael , FEISTE, Kurt, Alan , VAN NORSTRAND, Albert, James, Jr. , HALL, Ronald
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/30181 , G06F9/30189 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3861
摘要： An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.
摘要翻译：提供了一种用于将处理器置于逐渐减速操作模式的问题单元。逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。处理器逐渐减速使处理器能够突破活动锁定状态。此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。说明性实施例的机制通过对较不严重的活动锁定条件采取小的性能影响并且仅当活锁状态更严重时才增加处理器性能影响，基于活动锁定状况的严重性来影响整体处理器性能。

26. 发明申请

WO2006112978A3 MICROPROCESSOR ACCESS OF OPERAND STACK AS A REGISTER FILE USING NATIVE INSTRUCTIONS 审中-公开
标题翻译：微处理器作为使用原始指令的寄存器文件的操作访问
公开(公告)号：WO2006112978A3
公开(公告)日：2007-06-21
申请号：PCT/US2006008991
申请日：2006-03-08
申请人： ATMEL CORP , STROM OYVIND , RENNO ERIK , MONSEN KRISTIAN
发明人： STROM OYVIND , RENNO ERIK , MONSEN KRISTIAN
IPC分类号： G06F9/22 , G06F9/40 , G06F9/44
CPC分类号： G06F9/30134 , G06F9/3016 , G06F9/30196 , G06F9/321 , G06F9/3861
摘要： A combined native (RISC or CISC) microprocessor and stack (Java) machine (10, 11, 13) are constructed so that Java VM instructions can be executed in hardware. Most Java instructions are executed directly (54) , while more complex Java instructions, such as those manipulating Java objects, are executed as native microcode (56) . In order for native microcode instructions to access the Java operand stack, a Java operand stack pointer (22; 102) points to the register file (15; 90) location that is the current top of the stack (ToS) , while a remap bit (RM) in the status register (101) indicates that registers specified in native instructions are remapped (90a) as the maximum Java operand stack pointer value minus the present value of the Java operand stack pointer.
摘要翻译：构建组合本机（RISC或CISC）微处理器和堆栈（Java）机器（10,11,13），使得可以在硬件中执行Java VM指令。大多数Java指令是直接执行的（54），而更复杂的Java指令（如操作Java对象的Java指令）作为本地微代码执行（56）。为了使本地微代码指令访问Java操作数堆栈，Java操作数堆栈指针（22; 102）指向作为堆栈（ToS）的当前顶部的寄存器文件（15; 90）位置，而重映射位状态寄存器（101）中的（RM）表示在本地指令中指定的寄存器被重新映射（90a），作为最大Java操作数堆栈指针值减去Java操作数堆栈指针的当前值。

27. 发明申请

WO2007063322A1 METHOD OF PROTECTING THE PIPELINE EXECUTION UNIT OF A MICROPROCESSOR BY APPLYING TRIPLE MODULAR REDUNDANCY TECHNIQUES 审中-公开
标题翻译：通过应用三重模块化冗余技术保护微处理器的管道执行单元的方法
公开(公告)号：WO2007063322A1
公开(公告)日：2007-06-07
申请号：PCT/GB2006/004492
申请日：2006-12-01
申请人： MIRA LIMITED , LOUGHBOROUGH UNIVERSITY , WARD, David, Dewick , FLINT, James, Alan , CHOULIARAS, Vassilios, Apostolos , TOULOUPIS, Emmanuel
发明人： WARD, David, Dewick , FLINT, James, Alan , CHOULIARAS, Vassilios, Apostolos , TOULOUPIS, Emmanuel
IPC分类号： G06F11/16 , G06F11/18 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/3867 , G06F11/181 , G06F11/183
摘要： Microprocessor with at least three identical pipeline execution units which uses Triple Modular Redundancy (TMR) techniques at each stage of the pipeline execution units to protect the microprocessor against transient faults. A faulty pipeline execution unit is temporarily disconnected.
摘要翻译：具有至少三个相同流水线执行单元的微处理器，其在流水线执行单元的每个阶段使用三重模块化冗余（TMR）技术，以保护微处理器免受瞬态故障的影响。故障流水线执行单元暂时断开连接。

28. 发明申请

WO2007057831A1 DATA PROCESSING METHOD AND APPARATUS 审中-公开
标题翻译：数据处理方法和装置
公开(公告)号：WO2007057831A1
公开(公告)日：2007-05-24
申请号：PCT/IB2006/054213
申请日：2006-11-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SMEETS, Jean-Paul, C., F., H. , LEANE, David, E. , KLOOSTERHUIS, Willem, E, . H.
发明人： SMEETS, Jean-Paul, C., F., H. , LEANE, David, E. , KLOOSTERHUIS, Willem, E, . H.
IPC分类号： G06F9/38
CPC分类号： G06F9/3826 , G06F9/3832 , G06F9/3861
摘要： A data processing apparatus comprises a register file (3) connected to an ALU (5) via an ALU input register (7). A feedback path (9) is provided for storing results generated by the ALU (5) in the register file (3). A bypass circuit, for example comprising multiplexers (11 and 13), is provided for effectively bypassing the register file (3), thus allowing the results of the ALU (5) to be forwarded directly to the input register (7) of the ALU (5), so that the register file (3) can be bypasses when the result of a first instruction is used as the operand of a second instruction during a subsequent processing cycle. A bypass control means (15) is provided for determining when the result of a first instruction is only used once by a second instruction, and the timing of the first and second instructions is such that an operand for the second instruction is provided by the bypass network. When the bypass control means (15) determines this to be the case, the bypass control means (15) is further adapted to prevent the result of the first instruction to be written to the register file. In this case the contents will not be used in the future anymore. The invention has the advantage of saving power, by omitting this write to the register file.
摘要翻译：数据处理装置包括经由ALU输入寄存器（7）连接到ALU（5）的寄存器文件（3）。提供反馈路径（9）用于将由ALU（5）生成的结果存储在寄存器文件（3）中。提供了一个旁路电路，例如包括多路复用器（11和13），用于有效地绕过寄存器文件（3），从而允许将ALU（5）的结果直接转发到ALU的输入寄存器（7）（5），使得当在后续处理周期中使用第一指令的结果作为第二指令的操作数时，寄存器堆（3）可以被旁路。提供旁路控制装置（15），用于确定第一指令的结果何时仅由第二指令使用一次，并且第一和第二指令的定时使得第二指令的操作数由旁路提供网络。当旁路控制装置（15）确定为这种情况时，旁路控制装置（15）还适于防止第一指令的结果被写入寄存器文件。在这种情况下，内容将不再被使用。本发明具有通过省略对寄存器文件的写入来省电的优点。

29. 发明申请

WO2005114441A3 MICROPROCESSOR ARCHITECTURE 审中-公开
标题翻译：微处理器架构
公开(公告)号：WO2005114441A3
公开(公告)日：2007-01-18
申请号：PCT/US2005017586
申请日：2005-05-19
申请人： ARC INTERNAT UK LTD , ARISTODEMOU ARIS , LIM SEOW CHUAN , FUHLER RICHARD , TEMPLE ARTHUR ROBERT , TAYLOR MORGYN , WONG KAR-LIK , HAKEWILL JAMES , TOPHAM NIGEL , HANSSON DANIEL
发明人： ARISTODEMOU ARIS , LIM SEOW CHUAN , FUHLER RICHARD , TEMPLE ARTHUR ROBERT , TAYLOR MORGYN , WONG KAR-LIK , HAKEWILL JAMES , TOPHAM NIGEL , HANSSON DANIEL
IPC分类号： G06F7/38 , G06F9/00 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/40 , G06F9/44 , G06F12/00 , G06F12/08 , G06F15/00 , G06F15/76 , G06F15/78 , H03M13/00
CPC分类号： G06F9/3861 , G06F5/01 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30149 , G06F9/30181 , G06F9/32 , G06F9/325 , G06F9/3802 , G06F9/3806 , G06F9/3816 , G06F9/3844 , G06F9/3846 , G06F9/3885 , G06F9/3897 , G06F11/3648 , G06F12/0802 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A microprocessor is provided having improved performance and characterized in the use of dynamic branch prediction, a unified cache debug unit, a 64 bit right only barrel shifter, a predictive pre-fetch memory pipeline and customizable processor extensions.
摘要翻译：提供了具有改进性能的微处理器，其特征在于使用动态分支预测，统一缓存调试单元，64位右侧桶形移位器，预测预取存储器流水线和可定制的处理器扩展。

30. 发明申请

WO2006057907A3 PRE-DECODE ERROR HANDLING VIA BRANCH CORRECTION 审中-公开
标题翻译：通过分支校正进行预解码错误处理
公开(公告)号：WO2006057907A3
公开(公告)日：2006-12-14
申请号：PCT/US2005041850
申请日：2005-11-18
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/318
CPC分类号： G06F9/3861 , G06F9/30152 , G06F9/3017 , G06F9/382
摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as "mispredicted not taken" with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.
摘要翻译：在其中指令在被存储在高速缓冲存储器中之前进行预解码的流水线处理器中，在流水线执行期间检测到不正确的预解码指令。相应的指令在高速缓存中无效，并且强制将该指令作为分支指令进行求值。特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被预测”。这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。重新读取的指令然后被正确地预解码，写入高速缓存并执行。

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