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21. 发明申请

WO2005041509A1 CHANNEL ESTIMATION USING PILOT SYMBOLS 审中-公开
标题翻译：使用引导符号进行信道估计
公开(公告)号：WO2005041509A1
公开(公告)日：2005-05-06
申请号：PCT/EP2003/010815
申请日：2003-09-30
申请人： TELECOM ITALIA S.P.A. , D'AMICO, Valeria , GRAZIANO, Maurizio , MELIS, Bruno , RUSCITTO, Alfredo
发明人： D'AMICO, Valeria , GRAZIANO, Maurizio , MELIS, Bruno , RUSCITTO, Alfredo
IPC分类号： H04L25/02
CPC分类号： H04L25/0204 , H04L25/0206 , H04L25/0232 , H04L25/0236
摘要： A system for estimating the transfer function of a transmission channel such as the downlink channel in a CDMA system over which a pilot signal (P-CPICH) and a data signal (DPCH) are transmitted. The system includes: - at least one estimator (21, 22, 27; 24, 23, 25) for producing first and second channel estimates from the pilot signal and the data signals, and - a combination node (26) for combining the first and second channel estimates to obtain final combined channel estimates. The system includes an interpolator module (25) adapted for interpolating the second channel estimates over a basic estimation reference time (T) to produce equal numbers of channel estimates over the basic estimation reference time (T) derived from the data signal and the pilot signal respectively, and, possibly - rate adaptation modules (23, 27) adapted for mapping the channel estimates on the basic estimation reference time (T). The combination node is a summation node (26) producing the final combined channel estimates as a sum (26) of the first channel estimates and the interpolated second channel estimates.
摘要翻译：一种用于估计发送导频信号（P-CPICH）和数据信号（DPCH）的CDMA系统中诸如下行链路信道之类的传输信道的传递函数的系统。该系统包括： - 用于从导频信号和数据信号产生第一和第二信道估计的至少一个估计器（21,22,27; 24,23,25），和 - 组合节点（26），用于将第一和第二渠道估计，以获得最终的组合渠道估计。该系统包括适于在基本估计基准时间（T）上内插第二信道估计以在从数据信号和导频信号导出的基本估计参考时间（T）上产生相等数目的信道估计的内插器模块（25）以及可能的速率自适应模块（23,27），其适于在基本估计参考时间（T）上映射信道估计。组合节点是产生作为第一信道估计和插值的第二信道估计的和（26）的最终组合信道估计的求和节点（26）。

22. 发明申请

WO2003017085A3 POWER RAISING CIRCUIT 审中-公开
公开(公告)号：WO2003017085A3
公开(公告)日：2003-02-27
申请号：PCT/IT2002/000539
申请日：2002-08-14
申请人： TELECOM ITALIA S.P.A. , ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
IPC分类号： G06F7/552
摘要： An iterative power raising circuit, such as a squarer (10) comprises a module (13, 14) able to subdivide the respective input signal (Z n ) into a first part (msb(Z n )) that is the power of 2 immediately lower than or equal to the input signal and a second part (Z n - msb(Z n )) corresponding to the difference between the respective input signal and the first part. A first component of the output signal is determined as the summation of squares of powers of 2 implemented by inserting zeros between the adjacent bits of the input binary signal (X). A shifter module (15) generates an additional component of the output signal through shift operations that implement multiplication operations for numbers that are powers of 2. The circuit operates according to a general iterative scheme and the number of steps in the iteration scheme is selectively controllable in order selectively to vary the precision with which the output value (Y) is calculated.

23. 发明申请

WO2003007195A3 SYSTEM AND METHOD FOR MAKING COMPLEX ELECTRONIC CIRCUITS 审中-公开
公开(公告)号：WO2003007195A3
公开(公告)日：2003-01-23
申请号：PCT/IT2002/000450
申请日：2002-07-09
申请人： TELECOM ITALIA S.P.A. , GARINO, Pierangelo , RICCIATO, Fabio , RUSCITTO, Alfredo , TUROLLA, Maura , VARRIALE, Antonio
发明人： GARINO, Pierangelo , RICCIATO, Fabio , RUSCITTO, Alfredo , TUROLLA, Maura , VARRIALE, Antonio
IPC分类号： G06F17/50
摘要： The present invention relates to a system (10) and method for making electronic circuits comprising elements or elementary circuit blocks which can be implemented either in the form of physical circuits, for instance FPGA, or in the form of firmware, for instance memorised on microprocessor. Thanks to the methodology used to describe the circuit blocks (26a, 26b) and their functional models (21), the system (10) and method allow to execute with a WS (11) and an emulator subsystem (30), in a single integrated environment, both the functional simulation of the model of complex electronic circuit and the emulation of the electronic circuit itself. Moreover, thanks to the characteristics of intrinsic congruence between the circuit blocks (26a, 26b) and their models (21), the emulation of the complex electronic circuit can be effected using alternatively circuit blocks implemented on the emulator subsystem either in the form of hardware (26a) or in the form of firmware (26b).

24. 发明申请

WO2009084051A1 MANAGEMENT OF A HYBRID COMMUNICATION NETWORK COMPRISING A CELLULAR NETWORK AND A LOCAL NETWORK 审中-公开
标题翻译：包含细胞网络和本地网络的混合通信网络的管理
公开(公告)号：WO2009084051A1
公开(公告)日：2009-07-09
申请号：PCT/IT2007/000928
申请日：2007-12-28
申请人： TELECOM ITALIA S.P.A. , FANTINI, Roberto , GALLO, Paolo , RUSCITTO, Alfredo
发明人： FANTINI, Roberto , GALLO, Paolo , RUSCITTO, Alfredo
IPC分类号： H04Q7/38 , H04Q7/32
CPC分类号： H04W48/18 , H04L5/006 , H04L67/32 , H04W28/0236 , H04W28/18 , H04W40/08 , H04W40/12 , H04W72/1226
摘要： Disclosed herein is a method of managing a hybrid network comprising a cellular network (3) and a local network (4) wherein a number of dual mode mobile terminals (7) are connectable to a base.station (10) of the cellular network (3) through a direct cellular link and are also connectable, one with respect to the other, through the local network (4) by means of a radio access technique. The method comprises the steps of computing a cost associated with a direct connection established along a path (A) extending from a selected mobile terminal to the base station (10) trough the cellular link only; computing a cost (C cg ) associated with at least one indirect connection established along a path (B) extending from said selected mobile terminal to said base station (10) trough the local network (4) and the cellular network (3) and selecting for data transmission the path that minimizes the cost.
摘要翻译：本文公开了一种管理包括蜂窝网络（3）和本地网络（4）的混合网络的方法，其中多个双模移动终端（7）可连接到蜂窝网络的基站（10）（10） 3）通过直接蜂窝链路，并且也可以通过无线电接入技术通过本地网络（4）彼此连接。该方法包括以下步骤：仅通过蜂窝链路来计算沿着从所选移动终端延伸到基站（10）的路径（A）建立的直接连接的成本; 计算与通过本地网络（4）和蜂窝网络（3）从所述选择的移动终端延伸到所述基站（10）的路径（B）建立的至少一个间接连接相关联的成本（Ccg），并且选择数据传输最小化成本的路径。

25. 发明申请

WO2007048427A1 METHOD AND SYSTEM FOR MULTIPLE ANTENNA COMMUNICATIONS USING MULTIPLE TRANSMISSION MODES, RELATED APPARATUS AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：使用多种传输模式的多天线通信的方法和系统，相关设备和计算机程序产品
公开(公告)号：WO2007048427A1
公开(公告)日：2007-05-03
申请号：PCT/EP2005/011529
申请日：2005-10-27
申请人： TELECOM ITALIA S.P.A. , PIRELLI & C. S.p.A. , MELIS, Bruno , RUSCITTO, Alfredo , SEMENZATO, Paolo , MELE, Renata , GRASSANO, Giuseppe
发明人： MELIS, Bruno , RUSCITTO, Alfredo , SEMENZATO, Paolo , MELE, Renata , GRASSANO, Giuseppe
IPC分类号： H04B7/06 , H04B7/08
CPC分类号： H04B7/0894 , H04B7/0671
摘要： A system for diversity processing a signal (INPUT) propagated via two diversity antennas (1, 2) includes: respective propagation paths for propagating two replicas of the signal (INPUT), these propagation paths being coupled to the two diversity antennas (1, 2), so that the replicas are propagated via different antennas (1, 2) ; a time variable delay element (16) for subjecting at least one of the replicas to a time variable delay; and a level adjusting element, such as an asymmetric 15 splitter (14) to produce a level imbalance (A) between the power levels of the replicas propagated via the two diversity antennas (1, 2).
摘要翻译：用于分集处理经由两个分集天线（1,2）传播的信号（INPUT）的系统包括：用于传播信号（INPUT）的两个副本的各个传播路径，这些传播路径耦合到两个分集天线（1,2）），使得副本通过不同的天线（1,2）传播; 时间可变延迟元件（16），用于对所述副本中的至少一个进行时间可变延迟; 以及电平调整元件，例如非对称15分路器（14），以在通过两个分集天线（1,2）传播的副本的功率电平之间产生电平不平衡（A）。

26. 发明申请

WO2004047328A1 MEMORY BASED DEVICE AND METHOD FOR CHANNEL ESTIMATION IN A DIGITAL COMMUNICATION RECEIVER 审中-公开
标题翻译：基于记忆的设备和数字通信接收机中信道估计的方法
公开(公告)号：WO2004047328A1
公开(公告)日：2004-06-03
申请号：PCT/EP2002/012815
申请日：2002-11-15
申请人： TELECOM ITALIA S.P.A. , STMICROELECTRONICS S.R.L. , ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , OSSOLI, Alessandro , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , OSSOLI, Alessandro , RUSCITTO, Alfredo
IPC分类号： H04B1/707
CPC分类号： H04B1/7093 , H04B1/7113 , H04B1/7117 , H04B2201/70707
摘要： A spread spectrum digital communication receiver, of the type comprising an input memory buffer (16) for storing samples of an input signal (y(k)) and a code generator circuit (30) for generating a re-generated user code, incorporates a device (24) for the estimation of a channel delay profile comprises: a basic correlator (32) having a first input (41) for sequentially reading from a memory location of the input memory buffer (16) a plurality of samples of the input signal (y(k)), a second input (43) for receiving from the code generator circuit (30) a re-generated user code, and an output terminal for generating, by means of a correlation operation between the plurality of samples of the input signal and the regenerated user code, a first value of the channel delay profile energy (DP(1)); and a memory controller circuit (36) for addressing said the memory buffer (16) so that the first input (41) of the basic correlator (32) is successively fed with the content of several memory locations of the memory buffer (16), each addressing operation corresponding to a new correlation operation of the basic correlator (32) for the computation of a new value of the channel delay profile energy (DP(l)).
摘要翻译：包括用于存储输入信号（y（k））的采样的输入存储器缓冲器（16）和用于生成重新生成的用户代码的代码生成器电路（30）的类型的扩展频谱数字通信接收机包括一个用于估计信道延迟分布的装置（24）包括：基本相关器（32），具有用于从输入存储器缓冲器（16）的存储器位置顺序读取输入信号的多个样本的第一输入端（41）（y（k）），用于从码发生器电路（30）接收重新生成的用户码的第二输入端（43），以及输出端子，用于通过所述多个采样输入信号和再生用户代码，信道延迟分布能量（DP（1））的第一值; 以及存储器控制器电路（36），用于寻址所述存储器缓冲器（16），使得所述基本相关器（32）的第一输入端（41）被连续地馈送到所述存储器缓冲器（16）的若干存储器位置的内容，每个寻址操作对应于用于计算信道延迟分布能量（DP（1））的新值的基本相关器（32）的新的相关操作。

27. 发明申请

WO2004047326A1 METHOD AND DEVICE FOR FINE SYNCHRONIZATION OF A DIGITAL TELECOMMUNICATION RECEIVER 审中-公开
标题翻译：用于数字电信接收机精细同步的方法和设备
公开(公告)号：WO2004047326A1
公开(公告)日：2004-06-03
申请号：PCT/EP2002/012813
申请日：2002-11-15
申请人： TELECOM ITALIA S.P.A. , STMICROELECTRONICS S.R.L. , ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , RUSCITTO, Alfredo
IPC分类号： H04B1/707
CPC分类号： H04B1/7085 , H04B1/70757
摘要： A method for the synchronization of a digital telecommunication receiver comprises the steps of: - storing a plurality of consecutive samples E-l, E, M, L, L+1 of an incoming spread spectrum signal in a delay line 56; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a first digitally controlled interpolator 26, an interpolated early sample (e) anticipating an optimal sampling time instant; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a second digitally controlled interpolator 24, an interpolated middle sample (m) corresponding to the optimal sampling time instant; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a third digitally controlled interpolator 28, an interpolated late sample (1) delayed with respect to the optimal sampling time instant; - calculating an error signal ξ as the difference between the energy of the symbols computed from the interpolated early sample (e) and the interpolated late (1) sample; - extracting the sign of the error signal ξ - accumulating the sign of the error signal ξ for the generation of control signals S E , S M , S L for controlling the interpolation phases of the digitally controlled interpolators used for determining the interpolated early (e), middle (m) and late (l) samples. The accumulated value has a positive saturation value of +4 and a negative saturation value of 4.
摘要翻译：一种用于数字电信接收机同步的方法包括以下步骤： - 在延迟线56中存储输入扩频信号的多个连续样本E-1，E，M，L，L + 1; - 通过第一数字控制内插器26来确定进入的扩频信号的连续采样之间的插值，预测最佳采样时刻的内插早期采样（e）; - 通过第二数字控制内插器24确定进入的扩频信号的连续采样之间的插值，对应于最佳采样时刻的内插中间采样（m）; - 通过第三数字控制内插器28确定进入的扩展频谱信号的连续样本之间的内插，相对于最佳采样时刻延迟的内插后采样（1）; 将误差信号xi计算为从插值的早期样本（e）和插值的深（1）样本计算的符号的能量之间的差; - 提取误差信号xi的符号 - 累积误差信号xi的符号以产生控制信号S> E <，S> M <，S> L <用于控制用于数字控制内插器的内插相位确定内插的早期（e），中（m）和晚（l）样本。累积值的正饱和值为+4，负饱和值为4。

28. 发明申请

WO2003017084A2 MULTIPLIER CIRCUIT 审中-公开
标题翻译： MULTIPLIER电路
公开(公告)号：WO2003017084A2
公开(公告)日：2003-02-27
申请号：PCT/IT2002/000540
申请日：2002-08-14
申请人： TELECOM ITALIA LAB S.P.A. , ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
IPC分类号： G06F7/52
CPC分类号： G06F7/523 , G06F2207/3852
摘要： An iterative multiplier circuit (10) comprises modules (15 to 18) that subdivide the respective input signals (Z n , J n ) into a first part (msb(Z n ), msb(J n )) that is the power of 2 immediately lower or equal to the input signal and a second part (Z n -msb(Z n ), J n - msb(J n )) corresponding to the difference between the input signal and the aforesaid first part. A shift module (19) generates a respective output signal through shift operations that implement the multiplication operation for numbers that are powers of 2. The circuit operates according to a general iterative scheme in which at each step three components of the output signal (X.Y) are computed, corresponding to the product of two numbers that are powers of 2 and to two products in which at least one of the factors is a power of 2. The number of steps in the iteration scheme is controllable, thus allowing to vary the accuracy with which the output value (X.Y) is calculated.
摘要翻译：迭代乘法器电路（10）包括将相应输入信号（Zn，Jn）细分为第二部分（msb（Zn），msb（Jn））的模块（15至18），其为2的功率立即下降或相等与输入信号和上述第一部分之间的差相对应的输入信号和第二部分（Zn-msb（Zn），Jn-msb（Jn））。移位模块（19）通过对作为功率为2的数字实施乘法运算的移位运算产生相应的输出信号。该电路根据通常的迭代方案运行，其中在每个步骤输出信号（XY）的三个分量被计算，对应于作为2的幂的两个数字的乘积和至少一个因子是2的幂的两个乘积。迭代方案中的步数可以被控制，从而允许改变精度计算输出值（XY）。

29. 发明申请

WO2003017085A2 POWER RAISING CIRCUIT 审中-公开
标题翻译：功率放大电路
公开(公告)号：WO2003017085A2
公开(公告)日：2003-02-27
申请号：PCT/IT2002/000539
申请日：2002-08-14
申请人： TELECOM ITALIA LAB S.P.A. , ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
IPC分类号： G06F7/552
CPC分类号： G06F7/552 , G06F2207/3852 , G06F2207/5523
摘要： An iterative power raising circuit, such as a squarer (10) comprises a module (13, 14) able to subdivide the respective input signal (Z n ) into a first part (msb(Z n )) that is the power of 2 immediately lower than or equal to the input signal and a second part (Z n - msb(Z n )) corresponding to the difference between the respective input signal and the first part. A first component of the output signal is determined as the summation of squares of powers of 2 implemented by inserting zeros between the adjacent bits of the input binary signal (X). A shifter module (15) generates an additional component of the output signal through shift operations that implement multiplication operations for numbers that are powers of 2. The circuit operates according to a general iterative scheme and the number of steps in the iteration scheme is selectively controllable in order selectively to vary the precision with which the output value (Y) is calculated.
摘要翻译：诸如平方器（10）的迭代功率提升电路包括能够将相应的输入信号（Zn）细分成第二部分（msb（Zn））的模块（13,14），其是2的功率，其立即低于或等于输入信号的第二部分（Zn-msb（Zn））和与第一部分之间的差相对应的第二部分（Zn-msb（Zn））。输出信号的第一分量被确定为通过在输入二进制信号（X）的相邻位之间插入零而实现的功率2的平方的和。移位器模块（15）通过对作为功率为2的数字执行乘法运算的移位运算产生输出信号的附加分量。该电路根据一般迭代方案运行，并且迭代方案中的步数可以选择性地控制以便有选择地改变计算出输出值（Y）的精度。

30. 发明申请

WO2003007195A2 SYSTEM AND METHOD FOR MAKING COMPLEX ELECTRONIC CIRCUITS 审中-公开
标题翻译：制造复杂电子电路的系统和方法
公开(公告)号：WO2003007195A2
公开(公告)日：2003-01-23
申请号：PCT/IT2002/000450
申请日：2002-07-09
申请人： TELECOM ITALIA LAB S.P.A. , GARINO, Pierangelo , RICCIATO, Fabio , RUSCITTO, Alfredo , TUROLLA, Maura , VARRIALE, Antonio
发明人： GARINO, Pierangelo , RICCIATO, Fabio , RUSCITTO, Alfredo , TUROLLA, Maura , VARRIALE, Antonio
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： The present invention relates to a system (10) and method for making electronic circuits comprising elements or elementary circuit blocks which can be implemented either in the form of physical circuits, for instance FPGA, or in the form of firmware, for instance memorised on microprocessor. Thanks to the methodology used to describe the circuit blocks (26a, 26b) and their functional models (21), the system (10) and method allow to execute with a WS (11) and an emulator subsystem (30), in a single integrated environment, both the functional simulation of the model of complex electronic circuit and the emulation of the electronic circuit itself. Moreover, thanks to the characteristics of intrinsic congruence between the circuit blocks (26a, 26b) and their models (21), the emulation of the complex electronic circuit can be effected using alternatively circuit blocks implemented on the emulator subsystem either in the form of hardware (26a) or in the form of firmware (26b).
摘要翻译：本发明涉及一种用于制造包括元件或元件电路块的电子电路的系统（10）和方法，所述元件或基本电路块可以以物理电路（例如FPGA）的形式或以固件的形式实现，例如存储在微处理器。由于用于描述电路块（26a，26b）及其功能模型（21）的方法，所以系统（10）和方法允许以单一的方式（WS）（11）和仿真器子系统（30）执行综合环境，复杂电子电路模型的功能仿真和电子电路本身的仿真。此外，由于电路块（26a，26b）和它们的型号（21）之间的固有一致性的特征，复合电子电路的仿真可以使用在仿真器子系统上实现的电路块或硬件形式的硬件（26a）或固件（26b）的形式。

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