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1. 发明申请

WO2004047328A1 MEMORY BASED DEVICE AND METHOD FOR CHANNEL ESTIMATION IN A DIGITAL COMMUNICATION RECEIVER 审中-公开
标题翻译：基于记忆的设备和数字通信接收机中信道估计的方法
公开(公告)号：WO2004047328A1
公开(公告)日：2004-06-03
申请号：PCT/EP2002/012815
申请日：2002-11-15
申请人： TELECOM ITALIA S.P.A. , STMICROELECTRONICS S.R.L. , ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , OSSOLI, Alessandro , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , OSSOLI, Alessandro , RUSCITTO, Alfredo
IPC分类号： H04B1/707
CPC分类号： H04B1/7093 , H04B1/7113 , H04B1/7117 , H04B2201/70707
摘要： A spread spectrum digital communication receiver, of the type comprising an input memory buffer (16) for storing samples of an input signal (y(k)) and a code generator circuit (30) for generating a re-generated user code, incorporates a device (24) for the estimation of a channel delay profile comprises: a basic correlator (32) having a first input (41) for sequentially reading from a memory location of the input memory buffer (16) a plurality of samples of the input signal (y(k)), a second input (43) for receiving from the code generator circuit (30) a re-generated user code, and an output terminal for generating, by means of a correlation operation between the plurality of samples of the input signal and the regenerated user code, a first value of the channel delay profile energy (DP(1)); and a memory controller circuit (36) for addressing said the memory buffer (16) so that the first input (41) of the basic correlator (32) is successively fed with the content of several memory locations of the memory buffer (16), each addressing operation corresponding to a new correlation operation of the basic correlator (32) for the computation of a new value of the channel delay profile energy (DP(l)).
摘要翻译：包括用于存储输入信号（y（k））的采样的输入存储器缓冲器（16）和用于生成重新生成的用户代码的代码生成器电路（30）的类型的扩展频谱数字通信接收机包括一个用于估计信道延迟分布的装置（24）包括：基本相关器（32），具有用于从输入存储器缓冲器（16）的存储器位置顺序读取输入信号的多个样本的第一输入端（41）（y（k）），用于从码发生器电路（30）接收重新生成的用户码的第二输入端（43），以及输出端子，用于通过所述多个采样输入信号和再生用户代码，信道延迟分布能量（DP（1））的第一值; 以及存储器控制器电路（36），用于寻址所述存储器缓冲器（16），使得所述基本相关器（32）的第一输入端（41）被连续地馈送到所述存储器缓冲器（16）的若干存储器位置的内容，每个寻址操作对应于用于计算信道延迟分布能量（DP（1））的新值的基本相关器（32）的新的相关操作。

2. 发明申请

WO2004047327A1 EARLY-LATE SYNCHRONIZER HAVING REDUCED TIMING JITTER 审中-公开
标题翻译：具有减少时序抖动的早期同步器
公开(公告)号：WO2004047327A1
公开(公告)日：2004-06-03
申请号：PCT/EP2002/012814
申请日：2002-11-15
申请人： TELECOM ITALIA S.P.A. , STMICROELECTRONICS S.R.L. , ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , RUSCITTO, Alfredo
IPC分类号： H04B1/707
CPC分类号： H04B1/7085 , H04B1/709
摘要： A device for maintaining fine alignment between an incoming spread spectrum signal and a locally generated code in a digital communication receiver comprises: - a delay line (56) for storing a plurality of consecutive samples (E-1, E, M, L, L+1) of the incoming spread spectrum signal; - three digitally controlled interpolators (24, 26, 28) for determining by interpolation between consecutive samples an interpolated early sample (e), an interpolated middle sample (m) and an interpolated late sample (1); - two correlators (30, 32) for calculating an error signal (ξ) as the difference between the energy of the symbols computed from the interpolated early (e) and late (1) samples; - a circuit for generating a control signal (S¿OUT?) for controlling the interpolation phase of the digitally controlled interpolator (24) for the early sample (e), and - a digital non-linear filter (68), for smoothing the control signal (S¿OUT?) of the interpolator (24) for the early sample (e), enabling the update operation of the control signal only when the absolute value (|ξ(n)|) of the error signal at a time instant n is smaller than the absolute value (|ξ(n-1)|) of the same error signal at a time instant n-1.
摘要翻译：一种用于在数字通信接收机中保持输入扩频信号与本地生成代码之间的精确对准的装置，包括： - 延迟线（56），用于存储多个连续样本（E-1，E，M，L，L +1）的入射扩频信号; - 三个数字控制内插器（24,26,28），用于通过内插的早期采样（e），内插中间样本（m）和插值后期样本（1）来确定连续采样之间的内插; - 用于计算误差信号（xi）的两个相关器（30,32）作为从内插的早期（e）和晚期（1）样本计算的符号的能量之间的差; - 用于产生用于控制用于早期采样（e）的数字控制内插器（24）的内插相位的控制信号（S _ OUT <）的电路，以及 - 数字非线性滤波器（68），用于平滑用于早期采样（e）的内插器（24）的控制信号（S _OUT？），使得只有当误差信号的绝对值（|| xi（n）||）时刻n小于在时刻n-1的相同误差信号的绝对值（|| xi（n-1）||）。

3. 发明申请

WO2004047326A1 METHOD AND DEVICE FOR FINE SYNCHRONIZATION OF A DIGITAL TELECOMMUNICATION RECEIVER 审中-公开
标题翻译：用于数字电信接收机精细同步的方法和设备
公开(公告)号：WO2004047326A1
公开(公告)日：2004-06-03
申请号：PCT/EP2002/012813
申请日：2002-11-15
申请人： TELECOM ITALIA S.P.A. , STMICROELECTRONICS S.R.L. , ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , RUSCITTO, Alfredo
IPC分类号： H04B1/707
CPC分类号： H04B1/7085 , H04B1/70757
摘要： A method for the synchronization of a digital telecommunication receiver comprises the steps of: - storing a plurality of consecutive samples E-l, E, M, L, L+1 of an incoming spread spectrum signal in a delay line 56; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a first digitally controlled interpolator 26, an interpolated early sample (e) anticipating an optimal sampling time instant; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a second digitally controlled interpolator 24, an interpolated middle sample (m) corresponding to the optimal sampling time instant; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a third digitally controlled interpolator 28, an interpolated late sample (1) delayed with respect to the optimal sampling time instant; - calculating an error signal ξ as the difference between the energy of the symbols computed from the interpolated early sample (e) and the interpolated late (1) sample; - extracting the sign of the error signal ξ - accumulating the sign of the error signal ξ for the generation of control signals S E , S M , S L for controlling the interpolation phases of the digitally controlled interpolators used for determining the interpolated early (e), middle (m) and late (l) samples. The accumulated value has a positive saturation value of +4 and a negative saturation value of 4.
摘要翻译：一种用于数字电信接收机同步的方法包括以下步骤： - 在延迟线56中存储输入扩频信号的多个连续样本E-1，E，M，L，L + 1; - 通过第一数字控制内插器26来确定进入的扩频信号的连续采样之间的插值，预测最佳采样时刻的内插早期采样（e）; - 通过第二数字控制内插器24确定进入的扩频信号的连续采样之间的插值，对应于最佳采样时刻的内插中间采样（m）; - 通过第三数字控制内插器28确定进入的扩展频谱信号的连续样本之间的内插，相对于最佳采样时刻延迟的内插后采样（1）; 将误差信号xi计算为从插值的早期样本（e）和插值的深（1）样本计算的符号的能量之间的差; - 提取误差信号xi的符号 - 累积误差信号xi的符号以产生控制信号S> E <，S> M <，S> L <用于控制用于数字控制内插器的内插相位确定内插的早期（e），中（m）和晚（l）样本。累积值的正饱和值为+4，负饱和值为4。

4. 发明申请

WO2003081862A1 INTERPOLATION FOR USE IN CHANNEL ESTIMATION 审中-公开
标题翻译：用于通道估计的插值
公开(公告)号：WO2003081862A1
公开(公告)日：2003-10-02
申请号：PCT/EP2003/002773
申请日：2003-03-17
申请人： TELECOM ITALIA S.P.A. , STMICROELECTRONICS S.R.L. , ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andreas , RUSCITTO, Alfredo , VALLE, Stefano , SIMONI, Lorena
发明人： ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andreas , RUSCITTO, Alfredo , VALLE, Stefano , SIMONI, Lorena
IPC分类号： H04L25/02
CPC分类号： H04L25/0232
摘要： A method for the estimation of the transfer function of a transmission channel in a receiving system of UMTS type envisages the computation of a plurality of channel coefficients, included among known channel coefficients corresponding to pilot symbols, through the reiteration of an interpolation algorithm, capable of calculating an intermediate point (Z, f(Z)) between a first extreme and a second extreme of a determined interval, the first extreme being formed by at least two known points and the second extreme being formed by at least one known point, the intermediate point to be calculated having as abscissa (Z) the abscissa value of the mean point between the points defining the interval rounded off to the integer closest to the first extreme, and having as ordinate (F(Z)) the arithmetic average between the ordinate of the known point of the second extreme and the ordinate of a point, chosen between the two known points of the first extreme, having a distance from the intermediate point equal to the distance between the intermediate point and the known point of the second extreme.
摘要翻译：用于估计UMTS类型的接收系统中的传输信道的传递函数的方法设想通过重复插值算法来计算包括在与导频符号相对应的已知信道系数之中的多个信道系数，能够计算确定间隔的第一极限和第二极限之间的中间点（Z，f（Z）），所述第一极值由至少两个已知点形成，所述第二极值由至少一个已知点形成，要计算的中间点具有横坐标（Z），将定义间隔的间隔的平均点的横坐标值舍入到最接近第一极限的整数，并且具有纵坐标（F（Z））之间的算术平均值在第二极端的已知点的纵坐标和在第一极端的两个已知点之间选择的点的纵坐标距离中间件的距离点等于中间点与第二极限的已知点之间的距离。

5. 发明申请

WO2003017084A3 MULTIPLIER CIRCUIT 审中-公开
公开(公告)号：WO2003017084A3
公开(公告)日：2003-02-27
申请号：PCT/IT2002/000540
申请日：2002-08-14
申请人： TELECOM ITALIA S.P.A. , ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
IPC分类号： G06F7/52
摘要： An iterative multiplier circuit (10) comprises modules (15 to 18) that subdivide the respective input signals (Z n , J n ) into a first part (msb(Z n ), msb(J n )) that is the power of 2 immediately lower or equal to the input signal and a second part (Z n -msb(Z n ), J n - msb(J n )) corresponding to the difference between the input signal and the aforesaid first part. A shift module (19) generates a respective output signal through shift operations that implement the multiplication operation for numbers that are powers of 2. The circuit operates according to a general iterative scheme in which at each step three components of the output signal (X.Y) are computed, corresponding to the product of two numbers that are powers of 2 and to two products in which at least one of the factors is a power of 2. The number of steps in the iteration scheme is controllable, thus allowing to vary the accuracy with which the output value (X.Y) is calculated.

6. 发明申请

WO2003017085A3 POWER RAISING CIRCUIT 审中-公开
公开(公告)号：WO2003017085A3
公开(公告)日：2003-02-27
申请号：PCT/IT2002/000539
申请日：2002-08-14
申请人： TELECOM ITALIA S.P.A. , ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
IPC分类号： G06F7/552
摘要： An iterative power raising circuit, such as a squarer (10) comprises a module (13, 14) able to subdivide the respective input signal (Z n ) into a first part (msb(Z n )) that is the power of 2 immediately lower than or equal to the input signal and a second part (Z n - msb(Z n )) corresponding to the difference between the respective input signal and the first part. A first component of the output signal is determined as the summation of squares of powers of 2 implemented by inserting zeros between the adjacent bits of the input binary signal (X). A shifter module (15) generates an additional component of the output signal through shift operations that implement multiplication operations for numbers that are powers of 2. The circuit operates according to a general iterative scheme and the number of steps in the iteration scheme is selectively controllable in order selectively to vary the precision with which the output value (Y) is calculated.

7. 发明申请

WO2003017085A2 POWER RAISING CIRCUIT 审中-公开
标题翻译：功率放大电路
公开(公告)号：WO2003017085A2
公开(公告)日：2003-02-27
申请号：PCT/IT2002/000539
申请日：2002-08-14
申请人： TELECOM ITALIA LAB S.P.A. , ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
IPC分类号： G06F7/552
CPC分类号： G06F7/552 , G06F2207/3852 , G06F2207/5523
摘要： An iterative power raising circuit, such as a squarer (10) comprises a module (13, 14) able to subdivide the respective input signal (Z n ) into a first part (msb(Z n )) that is the power of 2 immediately lower than or equal to the input signal and a second part (Z n - msb(Z n )) corresponding to the difference between the respective input signal and the first part. A first component of the output signal is determined as the summation of squares of powers of 2 implemented by inserting zeros between the adjacent bits of the input binary signal (X). A shifter module (15) generates an additional component of the output signal through shift operations that implement multiplication operations for numbers that are powers of 2. The circuit operates according to a general iterative scheme and the number of steps in the iteration scheme is selectively controllable in order selectively to vary the precision with which the output value (Y) is calculated.
摘要翻译：诸如平方器（10）的迭代功率提升电路包括能够将相应的输入信号（Zn）细分成第二部分（msb（Zn））的模块（13,14），其是2的功率，其立即低于或等于输入信号的第二部分（Zn-msb（Zn））和与第一部分之间的差相对应的第二部分（Zn-msb（Zn））。输出信号的第一分量被确定为通过在输入二进制信号（X）的相邻位之间插入零而实现的功率2的平方的和。移位器模块（15）通过对作为功率为2的数字执行乘法运算的移位运算产生输出信号的附加分量。该电路根据一般迭代方案运行，并且迭代方案中的步数可以选择性地控制以便有选择地改变计算出输出值（Y）的精度。

8. 发明申请

WO2003017084A2 MULTIPLIER CIRCUIT 审中-公开
标题翻译： MULTIPLIER电路
公开(公告)号：WO2003017084A2
公开(公告)日：2003-02-27
申请号：PCT/IT2002/000540
申请日：2002-08-14
申请人： TELECOM ITALIA LAB S.P.A. , ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
IPC分类号： G06F7/52
CPC分类号： G06F7/523 , G06F2207/3852
摘要： An iterative multiplier circuit (10) comprises modules (15 to 18) that subdivide the respective input signals (Z n , J n ) into a first part (msb(Z n ), msb(J n )) that is the power of 2 immediately lower or equal to the input signal and a second part (Z n -msb(Z n ), J n - msb(J n )) corresponding to the difference between the input signal and the aforesaid first part. A shift module (19) generates a respective output signal through shift operations that implement the multiplication operation for numbers that are powers of 2. The circuit operates according to a general iterative scheme in which at each step three components of the output signal (X.Y) are computed, corresponding to the product of two numbers that are powers of 2 and to two products in which at least one of the factors is a power of 2. The number of steps in the iteration scheme is controllable, thus allowing to vary the accuracy with which the output value (X.Y) is calculated.
摘要翻译：迭代乘法器电路（10）包括将相应输入信号（Zn，Jn）细分为第二部分（msb（Zn），msb（Jn））的模块（15至18），其为2的功率立即下降或相等与输入信号和上述第一部分之间的差相对应的输入信号和第二部分（Zn-msb（Zn），Jn-msb（Jn））。移位模块（19）通过对作为功率为2的数字实施乘法运算的移位运算产生相应的输出信号。该电路根据通常的迭代方案运行，其中在每个步骤输出信号（XY）的三个分量被计算，对应于作为2的幂的两个数字的乘积和至少一个因子是2的幂的两个乘积。迭代方案中的步数可以被控制，从而允许改变精度计算输出值（XY）。

9. 发明申请

WO2006007871A1 METHOD FOR COMPRESSING A VECTOR CODEBOO, METHOD AND DEVICE FOR COMPRESSING DATA, AND DISTRIBUTED SPEECH RECOGNTION SYSTEM 审中-公开
标题翻译：用于压缩矢量代码的方法，用于压缩数据的方法和设备以及分布式语音识别系统
公开(公告)号：WO2006007871A1
公开(公告)日：2006-01-26
申请号：PCT/EP2004/008372
申请日：2004-07-23
申请人： TELECOM ITALIA S.P.A. , FODRINI, Maurizio , ETTORRE, Donato , BOLLANO, Gianmario
发明人： FODRINI, Maurizio , ETTORRE, Donato , BOLLANO, Gianmario
IPC分类号： G10L15/28
CPC分类号： G10L15/30
摘要： A method for compressing data, said data being represented by an input vector having Q features, wherein Q is an integer higher than 1, the method for compressing data comprising the steps of 1) providing a vector codebook comprising sub-sets of indexed Q-feature reference vectors and threshold values associated with said sub-sets for a prefixed feature; 2) identifying a sub-set of reference vectors among said sub-sets by progressively comparing the value of a feature of the input vector - which corresponds to said prefixed feature - with the threshold values associated with said--sub-sets; 3) identifying the reference vector which - within the sub-set identified in step 2) - provides the lowest distortion with respect to the input vector.
摘要翻译：一种用于压缩数据的方法，所述数据由具有Q特征的输入向量表示，其中Q是高于1的整数，所述压缩数据的方法包括以下步骤：1）提供矢量码本，其包括索引Q- 特征参考矢量和与前缀特征的所述子集相关联的阈值; 2）通过将与所述前缀特征相对应的输入向量的特征的值逐渐比较与所述子集相关联的阈值，来识别所述子集中的参考矢量的子集; 3）识别在步骤2）中识别的子集内 - 相对于输入向量提供最低失真的参考矢量。

10. 发明申请

WO2005050623A1 METHOD AND CIRCUIT FOR NOISE ESTIMATION, RELATED FILTER, TERMINAL AND COMMUNICATION NETWORK USING SAME, AND COMPUTER PROGRAM PRODUCT THEREFOR 审中-公开
标题翻译：用于噪声估计的方法和电路，相关滤波器，使用其的终端和通信网络及其计算机程序产品
公开(公告)号：WO2005050623A1
公开(公告)日：2005-06-02
申请号：PCT/EP2003/012629
申请日：2003-11-12
申请人： TELECOM ITALIA S.P.A. , BOLLANO, Gianmario , ETTORRE, Donato , POUSAS NAVARRO, Rodrigo
发明人： BOLLANO, Gianmario , ETTORRE, Donato , POUSAS NAVARRO, Rodrigo
IPC分类号： G10L21/02
CPC分类号： G10L21/0208
摘要： A filter such as a Wiener filter for noise reduction in a signal, such as a speech signal, affected by background noise includes a circuit (50) for determining values of an update function relating new value of estimated noise power (P noise-New ) to a previous value of estimated noise power (P noise ), the update function being a function of said previous estimated noise power (P noise ) and a mean input power spectral density (P IN-PSD ). The circuit (50) includes a look-up table (30) having values for the update function stored therein with the previous value of estimated noise power (P noise ) and the mean input power spectral density (P in _PSD ) as a first and a second search entry, respectively. These search entries are entered via an input module (10) and exploited by search circuitry (12 to 28) associated with the look-up table (30) for selectively searching values for the update function in the look-up table (30). The search is preferably carried out on the basis of an index (26) computed starting from said first and second search entries.
摘要翻译：诸如用于噪声降低的维纳滤波器的滤波器（例如语音信号）受背景噪声的影响包括：电路（50），用于确定将估计噪声功率的新值（Pnoise-New）与估计噪声功率（Pnoise）的先前值，更新功能是所述先前估计噪声功率（Pnoise）和平均输入功率谱密度（PIN-PSD）的函数。电路（50）包括具有存储在其中的具有估计噪声功率（Pnoise）的前一值和平均输入功率谱密度（Pin_PSD）的值作为第一和第二的查找表（30）搜索条目。这些搜索条目经由输入模块（10）输入，并且由与查找表（30）相关联的搜索电路（12至28）利用，用于选择性地搜索查找表（30）中的更新功能的值。搜索优选地基于从所述第一和第二搜索条目开始计算的索引（26）来执行。

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