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    • 4. 发明申请
    • METHOD AND SYSTEM FOR ACCESS CONTROL AND DATA PROTECTION IN DIGITAL MEMORIES, RELATED DIGITAL MEMORY AND COMPUTER PROGRAM PRODUCT THEREFOR
    • 数字存储器中的访问控制和数据保护的方法和系统,相关的数字存储器和计算机程序产品
    • WO2006066604A8
    • 2007-07-05
    • PCT/EP2004014611
    • 2004-12-22
    • TELECOM ITALIA SPABIANCO ALBERTOCOLAZZO LAURARICCIATO FABIOTUROLLA MAURAVARRIALE ANTONIO
    • BIANCO ALBERTOCOLAZZO LAURARICCIATO FABIOTUROLLA MAURAVARRIALE ANTONIO
    • G06F1/00
    • G06Q20/3555G06F12/0223G06F12/1466G06F12/1491G06F21/78G06Q20/341G06Q20/35765G07F7/1008
    • A digital memory (50 to 70), such as a memory card for mobile communication equipment, is adapted to be accessed by a plurality of users and have protected data stored therein. The memory (50 to 70) is dynamically partitionable in private memory areas (68) for storing data therein and has associated a secrecy tool (58 to 62) for securely allocating to the users respective private memory areas (68) and permitting the users to access the respective private areas (68) via a secure session channel to perform read/write commands (20 to 28) in said respective private areas. Typically, the memory/card includes: a card interface controller (50) for managing a physical communication layer between the digital memory and external host equipment, an internal memory (68) having associated a hardware lock (66) to control access to the internal memory (68), a set of cryptographic modules (58, 60, 52) to manage the secure session channel between the users and said digital memory, and a memory certificate (70) for certifying a 25 public key associated with the digital memory.
    • 诸如用于移动通信设备的存储卡的数字存储器(50至70)适于被多个用户访问并且具有存储在其中的保护数据。 存储器(50至70)可在专用存储器区域(68)中动态分区,用于在其中存储数据,并且具有与秘密工具(58至62)相关联的用于对用户安全分配各自的专用存储器区域(68)并允许用户 经由安全会话信道访问相应的专用区域(68),以在所述各个私人区域中执行读/写命令(20至28)。 通常,存储器/卡包括:卡接口控制器(50),用于管理数字存储器和外部主机设备之间的物理通信层;内部存储器(68),其具有关联硬件锁(66)以控制对内部 存储器(68),用于管理用户和所述数字存储器之间的安全会话通道的一组加密模块(58,60,52)以及用于证明与数字存储器相关联的25个公共密钥的存储器证书(70)。
    • 5. 发明申请
    • METHOD OF TRANSFERRING DATA IN AN ELECTRONIC CIRCUIT, ELECTRONIC CIRCUIT AND RELATING DEVICE
    • 在电子电路中传输数据的方法,电子电路及相关设备
    • WO2003019395A1
    • 2003-03-06
    • PCT/IT2002/000549
    • 2002-08-26
    • TELECOM ITALIA LAB S.P.A.BRAGAGNINI, AndreaGARINO, PerangeloTUROLLA, MauraVARRIALE, Antonio
    • BRAGAGNINI, AndreaGARINO, PerangeloTUROLLA, MauraVARRIALE, Antonio
    • G06F13/28
    • G06F13/28
    • The present invention is related to a method of transferring data in an electronic circuit (10) incorporating a control unit or CPU (21), first circuit blocks (41) and second circuit blocks (61) interconnected by means of a BUS (24). The method and the relating circuit envisage the use of interface devices (45a) and/or (45b), associated to respective circuit blocks, and capable of managing the direct transfer of data from the first block (41) to the second block (61), or vice-versa, without the control by the CPU (21) during such a transfer. For the purpose of this method, and relating circuit (101), interface device (45a) must be, able to intercept control commands issued by CPU (21) and to directly manage the data transfer from the first block (41) to the second block (61) .Thus, the method and the circuit (101), and the interface device (45a) make it possible to considerably reduce the load of CPU 21, BUS 24 and electronic circuit (101) as well.
    • 本发明涉及一种在包含控制单元或CPU(21)的电子电路(10)中传送数据的方法,通过BUS(24)互连的第一电路块(41)和第二电路块(61) 。 该方法和相关电路设想使用与相应电路块相关联的接口设备(45a)和/或(45b),并且能够管理数据从第一块(41)到第二块(61)的直接传送 ),反之亦然,而在这种传送期间没有CPU(21)的控制。 为了该方法和相关电路(101),接口装置(45a)必须能够拦截由CPU(21)发出的控制命令并且直接管理从第一块(41)到第二块 因此,该方法和电路(101)以及接口装置(45a)也可以显着地降低CPU21,BUS24和电子电路(101)的负载。
    • 9. 发明申请
    • A METHOD FOR DIRECT MEMORY ACCESS, RELATED ARCHITECTURE AND COMPUTER PROGRAM PRODUCT
    • 直接存储器访问的方法,相关的架构和计算机程序产品
    • WO2004053708A1
    • 2004-06-24
    • PCT/EP2002/013847
    • 2002-12-06
    • TELECOM ITALIA S.P.A.BRAGAGNINI, AndreaVARRIALE, Antonio
    • BRAGAGNINI, AndreaVARRIALE, Antonio
    • G06F13/28
    • G06F13/28
    • A method of exchanging data within a direct memory access (DMA) arrangement including a plurality of IP blocks (A, B, C) includes the step of associating with the IP blocks (A, B, C) respective DMA modules (IDMA A, IDMA B, IDMA C), each DMA module including an input buffer (11A, 11B, 11C) and an output buffer (12A, 12B, 12C). The DMA modules (IDMA A, IDMA B, IDMA C) are coupled over a data transfer facility (BUS) in a chain arrangement wherein each DMA module has at least one of its output buffer (12A, 12B) coupled to the input buffer (11B, 11C) of another DMA module downstream in the chain and its input buffer (11B, 11C) coupled to the output buffer (12A, 12B) of another DMA module upstream in the chain. The DMA modules interact with the respective IP blocks (A, B, C) by writing data from the input buffer (11A, 11B, 11C) of the IDMA module into the respective IP block (A, B, C) and reading data from the respective IP block (A, B, C) into the output buffer (12A, 12B, 12C) of the DMA module. The input (11A, 11B, 11C) and output (12A, 12B, 12C) buffers in the various DMA module are operated in such a way that; - writing of data from the input buffer (11A, 11B, 11C) of the DMA module into the respective IP block (A, B, C) is started when the input buffer (11A, 11B, 11C) is at least partly filled with data; - when said reading of data from the respective IP block (A, B, C) into the output buffer of the DMA module is completed, the data in the output buffer are transferred to the input buffer (11B, 11C) of the DMA module downstream in the chain or, in the case of last DMA module in the chain are provided as output data.
    • 在包括多个IP块(A,B,C)的直接存储器访问(DMA)布置中交换数据的方法包括与IP块(A,B,C)相关联的各个DMA模块(IDMA A, IDMA B,IDMA C),每个DMA模块包括输入缓冲器(11A,11B,11C)和输出缓冲器(12A,12B,12C)。 DMA模块(IDMA A,IDMA B,IDMA C)通过链路布置的数据传输设备(BUS)耦合,其中每个DMA模块具有耦合到输入缓冲器的至少一个输出缓冲器(12A,12B) 链条下游的另一DMA模块(11B,11C)及其输入缓冲器(11B,11C)耦合到链路上游另一个DMA模块的输出缓冲器(12A,12B)。 DMA模块通过将IDMA模块的输入缓冲器(11A,11B,11C)的数据写入相应的IP模块(A,B,C)和数据读取数据从而与相应的IP模块(A,B,C)进行交互 各自的IP块(A,B,C)到DMA模块的输出缓冲器(12A,12B,12C)中。 各种DMA模块中的输入(11A,11B,11C)和输出(12A,12B,12C)缓冲器的操作方式如下: 当所述输入缓冲器(11A,11B,11C)至少部分地被填充有:将所述DMA模块的输入缓冲器(11A,11B,11C)的数据写入相应的IP块(A,B,C) 数据; - 当从各个IP块(A,B,C)到DMA模块的输出缓冲器的数据读取完成时,输出缓冲器中的数据被传送到DMA模块的输入缓冲器(11B,11C) 在链中的下游,或者在链中的最后一个DMA模块的情况下提供输出数据。