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21. 发明申请

WO2011016793A3 METHODS AND SYSTEMS FOR CHECKING RUN-TIME INTEGRITY OF SECURE CODE 审中-公开
标题翻译：检查安全码的运行时间完整性的方法和系统
公开(公告)号：WO2011016793A3
公开(公告)日：2011-07-14
申请号：PCT/US2009050556
申请日：2009-07-14
申请人： QUALCOMM INC , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW , MILLENDORF STEVEN M
发明人： BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW , MILLENDORF STEVEN M
IPC分类号： G06F21/00
CPC分类号： G06F12/145 , G06F12/1027 , G06F21/52 , G06F21/54 , G06F21/575 , G06F21/629 , G06F21/71 , G06F21/74 , G06F21/79 , G06F21/81 , G06F2221/2105 , G06F2221/2141
摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.
摘要翻译：公开了用于防止旨在用非真实的，不安全的代码替代经认证的安全代码并使用CPU存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目被保存在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。指示许可的TLB许可条目为无效导致访问页面的按需认证。认证后，TLB中的许可条目被更新以反映该页面已被认证。作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。

22. 发明申请

WO2009015326A3 METHOD AND APPARATUS FOR ADAPTIVE VOLTAGE SCALING BASED ON INSTRUCTION USAGE 审中-公开
标题翻译：基于指令使用的自适应电压缩放的方法和装置
公开(公告)号：WO2009015326A3
公开(公告)日：2009-08-13
申请号：PCT/US2008071155
申请日：2008-07-25
申请人： QUALCOMM INC , HOFMANN RICHARD GERARD , BRIDGES JEFFREY TODD
发明人： HOFMANN RICHARD GERARD , BRIDGES JEFFREY TODD
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.
摘要翻译：不同的软件应用可以使用具有比处理器复合体的最坏情况关键时序路径更少的关键时序路径的一组指令。对于这样的应用，电源电压可能会降低，同时仍然保持必要的时钟频率以满足应用的性能要求。为了降低电源电压，使用自适应电压缩放方法。从多个关键路径中选择关键路径用于对仿真逻辑进行分析以确定片上功能操作期间所选关键路径的属性。选定的关键路径代表了在程序执行期间要运行的最坏情况关键路径。在片上功能操作期间，响应于属性来控制电压，其中电压向与多个关键路径相关联的电源域供电。基于指令集的使用，电压的降低可降低功耗，从而延长电池寿命。

23. 发明申请

WO2016039966A3 AUTOMATIC CALIBRATION CIRCUITS FOR OPERATIONAL CALIBRATION OF CRITICAL-PATH TIME DELAYS IN ADAPTIVE CLOCK DISTRIBUTION SYSTEMS, AND RELATED METHODS AND SYSTEMS 审中-公开
标题翻译：用于自适应时钟配电系统中的临界路径时延的操作校准的自动校准电路及相关的方法和系统
公开(公告)号：WO2016039966A3
公开(公告)日：2016-05-12
申请号：PCT/US2015046512
申请日：2015-08-24
申请人： QUALCOMM INC
发明人： BOWMAN KEITH ALAN , BRIDGES JEFFREY TODD , RAINA SARTHAK , KOLLA YESHWANT NAGARAJ , JEONG JIHOON , ATALLAH FRANCOIS IBRAHIM , FLEDERBACH WILLIAM ROBERT , FISCHER JEFFREY HERBERT
IPC分类号： H03K5/156 , G06F1/10 , H03K5/134
CPC分类号： H03K5/13 , G06F1/10 , H03K5/134 , H03K5/156 , H03K2005/00019
摘要： Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.
摘要翻译：用于自适应时钟分配系统中的关键路径时间延迟的操作校准的自动校准电路以及相关的方法和系统被公开。自适应时钟分配系统包括可调长度延迟电路，用于延迟提供给时钟电路的时钟信号的分布，以防止在向时钟电路供电的电源中发生电压下降之后时钟电路的时序裕度劣化。自适应时钟分配系统还包括动态变化监视器，以响应于电源中的电压下降而降低提供给时钟电路的延迟时钟信号的频率，使得时钟电路在电压期间不超过其性能极限下垂。在自适应时钟分配系统中提供自动校准电路，以根据时钟电路的操作条件和环境条件来校准操作期间的动态变化监测器。

24. 发明申请

WO2014022575A2 SYNTHESIZING INTERMEDIATE PERFORMANCE LEVELS IN INTEGRATED CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：综合集成电路中的中间性能水平以及相关处理器系统，方法和计算机可读介质
公开(公告)号：WO2014022575A2
公开(公告)日：2014-02-06
申请号：PCT/US2013053051
申请日：2013-07-31
申请人： QUALCOMM INC
发明人： BRIDGES JEFFREY TODD , KOLLA YESHWANT NAGARAJ , PATEL SANJAY B
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3234 , G06F1/3296 , Y02B60/1217 , Y02B60/1285 , Y02D10/126 , Y02D10/172
摘要： Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a synthesized performance level setting circuit receives an input indicating a synthesized performance mode. The circuit generates a power source selection output to select a first power source providing power to an integrated circuit functional block at a first voltage level, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block, for a first predefined time interval. The circuit also generates the power source selection output to select a second power source to provide power at a second voltage level lower than the first voltage level, and generate the clock frequency setting output to select a second clock frequency associated with the second voltage level to clock the functional block, for a second predefined time interval.
摘要翻译：公开了集成电路以及相关处理器系统，方法和计算机可读介质中的中间性能水平的综合。在一个实施例中，合成性能等级设置电路接收指示合成演出模式的输入。电路产生电源选择输出以选择在第一电压电平向集成电路功能块提供电力的第一电源，并且产生时钟频率设置输出，以选择与第一电压电平相关联的第一时钟频率以对功能块，用于第一预定时间间隔。电路还产生电源选择输出以选择第二电源以在低于第一电压电平的第二电压电平提供电力，并且产生时钟频率设置输出以选择与第二电压电平相关联的第二时钟频率对功能块进行计时，第二预定时间间隔。

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