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11. 发明申请

WO2007024567A3 CONTROLLED DEPTH ETCHED VIAS 审中-公开
公开(公告)号：WO2007024567A3
公开(公告)日：2007-03-01
申请号：PCT/US2006/031846
申请日：2006-08-16
申请人： LITTON SYSTEMS, INC. , MURRY, Thomas
发明人： MURRY, Thomas
IPC分类号： H05K1/11 , H01R12/04 , H01K3/10
摘要： A printed circuit board (20) includes a sub-assembly having dielectric (22) and conductive layers (24). A hole (26) extends into the sub-assembly. Metal plating (32) is applied on a barrel (27) of the hole (26). A conductive layer (32) and an etch resist (34) are applied to a first photoresist (30) on the hole barrel (27). The first photoresist (30) is removed and a second photoresist (36) is applied leaving areas to be controlled depth etched exposed. The exposed areas (38) are chemically etched. The second layer of photoresist (36) is removed and a second chemical etch operation is performed to define previously plated features (40) on the sub-assembly (20). The etch resist (34) is then removed.

12. 发明申请

WO2004082879A3 CONVEYORIZED BLIND MICROVIA LASER DRILLING SYSTEM 审中-公开
公开(公告)号：WO2004082879A3
公开(公告)日：2004-09-30
申请号：PCT/US2004/007987
申请日：2004-03-12
申请人： LASERVIA CORPORATION , BURGESS, Larry, W.
发明人： BURGESS, Larry, W.
IPC分类号： H01K3/10
摘要： A laser drilling system for drilling blind vias in printed circuit board panels, multichip modules and chipscale packages with top and bottom surfaces and which include multiple dielectric polymer and metal layers. The system includes a first laser module comprising a laser able to form at least one via per pulse through one or more polymer layers. The vias are circular or non-circular in shape. An articulated arm is adapted to move at a speed of about 200 inches per second and at an acceleration of about 5 g's or more. A beam delivery unit is attached to the articulated arm and a conveyor adapted to move panels at a constant speed. The first laser module positioned on a separate track from the conveyor moves at a faster rate than the conveyor to drill the top surface.

13. 发明申请

WO00068972A3 METHOD OF CREATING AN ELECTRICAL INTERCONNECT DEVICE BEARING AN ARRAY OF ELECTRICAL CONTACT PADS 审中-公开
标题翻译：创建连接电气接触垫阵列的电气互连装置的方法
公开(公告)号：WO00068972A3
公开(公告)日：2001-06-28
申请号：PCT/US2000/013140
申请日：2000-05-12
IPC分类号： G01R31/26 , G01R1/073 , H01L23/498 , H05K1/02 , H05K1/11 , H05K3/00 , H05K3/40 , H05K3/46 , B05D5/06 , B32B31/20 , H01K3/10 , H05B33/02 , H05B33/10 , H05K3/36
CPC分类号： H01L23/49838 , H01L23/49822 , H01L2924/0002 , H05K1/0219 , H05K1/0269 , H05K1/112 , H05K3/0008 , H05K3/0035 , H05K3/0082 , H05K3/4652 , H05K2201/0358 , H05K2201/09227 , H05K2201/09918 , H05K2201/10734 , H05K2203/107 , Y10T29/49002 , Y10T29/49126 , Y10T29/49139 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T29/49213 , Y10T29/5313 , H01L2924/00
摘要： A method of constructing a planar array (10) of electrical contact pads (12) is disclosed, comprising the following steps. First, providing a set of dielectric layers (110, 112, 114, 116) each having two major surfaces and forming a set of first conductive paths (120) on a first major surfaces (110a, 112a, 114a, 116a). Second, forming a set of second conductive paths (122) on a second major surface (110b, 112b, 114b, 116b). Third, joining the set of dielectric layers (110a, 112a, 114a, 116a). Forth, forming an array (10) of first and second electrical contact pads (12) on the top surface. Fifth and finally, forming a set of plated vias (138) to connect each first electrical contact pad (12) to a first conductive path (12) and each second electrical contact pad (12) to a second conductive path (122).
摘要翻译：公开了一种构造电接触焊盘（12）的平面阵列（10）的方法，包括以下步骤。首先，提供一组各自具有两个主表面并且在第一主表面（110a，112a，114a，116a）上形成一组第一导电路径（120）的电介质层（110,112,114,116）。第二，在第二主表面（110b，112b，114b，116b）上形成一组第二导电路径（122）。第三，接合该组电介质层（110a，112a，114a，116a）。第四，在顶表面上形成第一和第二电接触焊盘（12）的阵列（10）。第五，最后，形成一组电镀通孔（138），以将每个第一电接触焊盘（12）与第一导电路径（12）和每个第二电接触焊盘（12）连接到第二导电路径（122）。

14. 发明申请

WO2011138621A1 COMPOSITE ELECTRODE AND METHOD OF MANUFACTURE THEREOF 审中-公开
标题翻译：复合电极及其制造方法
公开(公告)号：WO2011138621A1
公开(公告)日：2011-11-10
申请号：PCT/GB2011/050888
申请日：2011-05-09
申请人： EPIGEM LIMITED , HARVEY, Thomas , RYAN, Timothy George
发明人： HARVEY, Thomas , RYAN, Timothy George
IPC分类号： H01L51/52 , H01L51/00 , H01K3/10 , H05K3/12
CPC分类号： H05K3/244 , H01L51/0023 , H01L51/003 , H01L51/0097 , H01L51/5212 , H01L2251/5338 , H01L2251/5361 , H05K2201/0108 , Y02E10/549 , Y02P70/521
摘要： The present invention provides a composite electrode and method of manufacturing such a composite electrode, the method comprising the steps of: providing a first substrate layer with an electrically conducting surface; providing a non-conducting curable material; providing a second substrate layer which has a surface relief pattern defining at least one retaining feature corresponding to a desired metal track pattern; forming a line of contact between the conducting carrier layer and at least a part of the surface relief pattern; depositing curable material onto at least part of the surface relief pattern or the electrically conducting surface along the line of contact; advancing the line of contact and curing the curable material through the second substrate layer; releasing the cured material from the surface relief pattern feature so as to leave behind a surface relief pattern on the conducting carrier layer; depositing a first metal layer onto the exposed regions of the electrically conducting surface of the conducting carrier layer and optionally deposition further metal layers on the first metal layer.
摘要翻译：本发明提供一种复合电极及其制造方法，该方法包括以下步骤：提供具有导电表面的第一基底层; 提供不导电的可固化材料; 提供具有限定对应于期望的金属轨道图案的至少一个保持特征的表面浮雕图案的第二基底层; 在所述导电载体层和所述表面浮雕图案的至少一部分之间形成接触线; 将可固化材料沿着所述接触线沉积到所述表面浮雕图案或所述导电表面的至少一部分上; 推进接触线并固化可固化材料通过第二基底层; 从表面浮雕图案特征释放固化材料，以便在导电载体层上留下表面浮雕图案; 将第一金属层沉积到导电载体层的导电表面的暴露区域上，以及任选地在第一金属层上沉积另外的金属层。

15. 发明申请

WO2005117508A3 PRINTED WIRING BOARD WITH CONDUCTIVE CONSTRAINING CORE INCLUDING RESIN FILLED CHANNELS 审中-公开
公开(公告)号：WO2005117508A3
公开(公告)日：2005-12-08
申请号：PCT/US2005/017150
申请日：2005-05-16
申请人： C-CORE TECHNOLOGIES, INC. , VASOYA, Kalu, K.
发明人： VASOYA, Kalu, K.
IPC分类号： H05K1/16 , H01K3/10
摘要： Printed wiring boards (100) and methods of manufacturing printed wiring boards are disclosed. In one aspect of the invention, the printed wiring boards include electrically conductive constraining cores (106) having at least one resin filled channel (116, 118). The resin filled channels perform a variety of functions that can be associated with electrical isolation and increased manufacturing yields.

16. 发明申请

WO2004088722A3 PRINTED WIRING BOARD, APPARATUS FOR ELECTRICALLY CONNECTING AN ELECTRONIC ELEMENT AND A SUBSTRATE, AND METHOD FOR MANUFACTURING A PRINTED WIRING BOARD 审中-公开
标题翻译：印刷电路板，用于电连接电子元件和基板的装置以及制造印刷电路板的方法
公开(公告)号：WO2004088722A3
公开(公告)日：2005-02-03
申请号：PCT/US2004009477
申请日：2004-03-29
申请人： SONY ELECTRONICS INC , MATSUDA YOSHINARI
发明人： MATSUDA YOSHINARI
IPC分类号： H05K1/09 , H05K3/28 , H05K3/34 , H05K3/40 , H01K3/10
CPC分类号： H05K3/3489 , H05K1/095 , H05K3/282 , H05K3/3447 , H05K3/4069 , H05K2201/09981 , H05K2203/0789 , H05K2203/1157
摘要： An apparatus for electrically connecting an electronic element (15) and a base (12) includes an electrode region and a terminal region (20) proximate the electrode region. A conductive paste (22) is deposited on at least a portion of the terminal region. The conductive paste has an oxidation-reduced region thereon, formed by application of an acid to the conductive paste. An oxidation-prevention layer is formed on the oxidation-reduced region by deposition of a flux on the oxidation-reduced region, application of a solder to the flux, and blowing of a heated gas by the solder. The oxidation-prevention layer is adapted to bond the electrode associated with the electronic element to the conductive paste by soldering, when the electrode is present in the electrode region.
摘要翻译：用于电连接电子元件（15）和基座（12）的装置包括电极区域和靠近电极区域的端子区域（20）。在端子区域的至少一部分上沉积导电膏（22）。导电性糊剂在其上具有氧化还原区域，其通过向导电膏施加酸而形成。通过在氧化还原区域上沉积焊剂，向焊剂上施加焊剂，并通过焊料吹入加热气体，在氧化还原区域上形成防氧化层。当电极存在于电极区域中时，氧化防止层适于通过焊接将与电子元件相关联的电极与导电膏接合。

17. 发明申请

WO2004021749A3 MANUFACTURE OF FLEXIBLE PRINTED CIRCUIT BOARDS 审中-公开
标题翻译：柔性印刷电路板的制造
公开(公告)号：WO2004021749A3
公开(公告)日：2004-07-01
申请号：PCT/US0326049
申请日：2003-08-20
申请人： PARLEX CORP
发明人： DEMASO ARTHUR , MCKENNEY DARRYL J , DOIRON LAUREA J JR
IPC分类号： H05K1/00 , H05K3/10 , H05K3/38 , H05K3/42 , H05K3/02 , H01K3/10
CPC分类号： H05K3/388 , H05K1/0393 , H05K3/108 , H05K3/426 , H05K2203/1545 , Y10T29/49156 , Y10T29/49165
摘要： A novel process is provided for the high speed fabrication of flexible printed circuit boards in continuous roll form and at a cost which is substantially less than the cost of existing fabrication processes. A web (30) of substrate material is supplied from a roll and one or both surfaces are sputter coated with a tie-coat (32) of Monel or chrome and a copper seed layer (34). The tie-coat (32) is typically of a thickness of about 50-300 angstroms, and the copper seed layer (34) has a thickness of about 200-4000 angstroms. Plated through holes are provided for double sided printed circuit boards, the holes being provided by laser or other suitable drilling equipment in an intended pattern on the substrate. A plating mask is provided with a negative image to allow subsequent selective electrodeposition of copper onto the unmasked areas of the substrate surfaces. The web is then passed through a continuous copper plating cell which provides a plate-up of copper on the unmasked areas of the seed layer. The web next undergoes a stripping process for the removable of the plating mask. Thereafter, a soft subtractive etching technique is employed to remove the sputtered layers of Monel and copper.
摘要翻译：提供了一种新颖的方法，用于以连续卷筒形式高速制造柔性印刷电路板，成本远低于现有制造工艺的成本。基材材料的网（30）从辊供应，并且一个或两个表面被溅射涂覆有Monel或铬和铜籽晶层（34）的粘结层（32）。连接层（32）通常具有约50-300埃的厚度，并且铜籽晶层（34）的厚度为约200-4000埃。为双面印刷电路板提供镀通孔，该孔由激光或其它合适的钻孔设备以基板上的预期图案提供。电镀掩模具有负像以允许随后将铜选择性电沉积到衬底表面的未掩模区域上。然后将纸幅通过连续的镀铜电池，其在种子层的未掩蔽区域上提供铜的平板。接下来，该网络经历剥离工艺以可移除电镀掩模。此后，采用软的消减蚀刻技术去除Monel和Copper的溅射层。

18. 发明申请

WO02056337A1 CHROMIUM ADHESION LAYER FOR COPPER VIAS IN LOW-K TECHNOLOGY 审中-公开
标题翻译：用于低K技术的铜箔的铬粘合层
公开(公告)号：WO02056337A1
公开(公告)日：2002-07-18
申请号：PCT/US2001/047815
申请日：2001-12-13
IPC分类号： H01K3/10 , H01L21/3205 , H01L21/768 , H01L23/50 , H01L23/52 , H01L23/532 , H05K3/02
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： In integrated circuits having copper interconnect (30, 50) and low-k interlayer dielectrics (40), a problem of open circuits after heat treatment was discovered and solved bz the use of a first liner layer of Cr (42), followed by a conformal liner layer of CVD TiN (46), followed in turn bz a final liner layer of Ta or TaN (48), thus improving adhesion between the via (50) and the underlying copper layer (30) while maintianing low resistance.
摘要翻译：在具有铜互连（30,50）和低k层间电介质（40）的集成电路中，发现并解决了热处理后的开路问题，并利用第一衬里层Cr（42），然后使用 CVD TiN（46）的共形内衬层，接着又是Ta或TaN（48）的最终内衬层，从而提高通孔（50）和下层铜层（30）之间的粘附性，同时保持低电阻。

19. 发明申请

WO00079849A1 HIGH PERFORMANCE BALL GRID ARRAY SUBSTRATES 审中-公开
标题翻译：高性能球栅阵列基板
公开(公告)号：WO00079849A1
公开(公告)日：2000-12-28
申请号：PCT/US2000/015885
申请日：2000-06-09
IPC分类号： H05K3/00 , H05K3/02 , H05K3/38 , H05K3/46 , H05K1/11 , H01K3/10 , H01R12/04 , H05K3/36
CPC分类号： H05K3/4655 , H05K3/0035 , H05K3/0038 , H05K3/022 , H05K3/025 , H05K3/386 , H05K3/4652 , H05K2201/0195 , H05K2201/0358 , H05K2203/066 , H05K2203/1152
摘要： Electronic substrates and printed circuit boards prepared from the electronic substrate, and more particularly, to methods and apparatuses for providing high density printed circuit substrates.
摘要翻译：从电子基板制备的电子基板和印刷电路板，更具体地说，涉及提供高密度印刷电路基板的方法和装置。

20. 发明申请

WO0026942A9 METHOD FOR PRODUCING FILLED VIAS IN ELECTRONIC COMPONENTS 审中-公开
标题翻译：在电子元件中生产填充的VIAS的方法
公开(公告)号：WO0026942A9
公开(公告)日：2000-10-19
申请号：PCT/US9925652
申请日：1999-11-02
申请人： COORS CERAMICS COMPANY
发明人： RITLAND MARCUS A , LANDIN STEVEN
IPC分类号： H01L23/10 , H01L23/498 , H05K1/03 , H05K3/40 , B32B3/10 , B05D5/12 , B32B31/00 , H01K3/10
CPC分类号： B23K26/382 , B23K26/389 , B23K26/40 , B23K2203/50 , B23K2203/52 , H01L23/10 , H01L23/49827 , H01L23/49883 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K3/4046 , H05K2201/10287 , H05K2201/10416 , Y10T29/49163 , Y10T29/49165 , Y10T156/1056 , Y10T428/24157 , H01L2924/00
摘要： The present invention relates to a process for producing filled vias (230) which are made of two components, a first component (240) which forms a bonding layer between the wall of the via and a second component (250) which forms the core of the via. Preferably, the two components solidify from a melt which includes two immiscible liquids. The first liquid is capable of wetting the wall of the via and the second liquid. The resulting product is also disclosed. Preferably the first component comprises a copper oxide and the second component comprises a conductive metal such as silver or copper.
摘要翻译：本发明涉及一种用于制造由两个部件制成的填充通孔（230）的方法，第一部件（240）在通孔的壁与第二部件（250）之间形成结合层，第二部件（250）形成通路。优选地，这两种组分从包含两种不混溶液体的熔体中固化。第一液体能够润湿通路的壁和第二液体。最终的产品也被披露。优选地，第一组分包含氧化铜，第二组分包含导电金属如银或铜。

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