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11. 发明申请

WO2004036747A1 デジタルフィルタの設計方法および装置、デジタルフィルタ設計用プログラム、デジタルフィルタ审中-公开
标题翻译：数字滤波器设计方法和设备，数字滤波器设计程序和数字滤波器
公开(公告)号：WO2004036747A1
公开(公告)日：2004-04-29
申请号：PCT/JP2003/013382
申请日：2003-10-20
申请人：有限会社ニューロソリューション , 小柳裕喜生
发明人：小柳裕喜生
IPC分类号： H03H17/06
CPC分类号： H03H17/06
摘要：非対称型の数値列をフィルタ係数Ｈ１～Ｈ３，Ｈ４～Ｈ６とする２つのユニットフィルタ１Ｌ１０，２Ｌ１０を縦続接続して対称型のユニットフィルタＬ１０”を構成し、これを縦続接続することによってフィルタ設計を行うようにすることにより、１種類のユニットフィルタＬ１０”の縦続接続だけで求めるデジタルフィルタの係数を自動的に得ることができるようにする。また、非対称型のフィルタ係数Ｈ１～Ｈ３，Ｈ４～Ｈ６として、対称型の数値列｛−１，０，９，１６，９，０，−１｝／３２をその中央で半分に分けたものを用いることにより、必要なタップ数が少なくなるようにするとともに、窓関数を用いる必要もなくし、得られるフィルタ特性に打ち切り誤差が生じないようにする。
摘要翻译：通过组合具有不对称数字序列的两个单元滤波器（1L10,2L10）作为滤波器系数（H1至H3和H4至H6）来设计对称单元滤波器（L10“），因此通过串联连接设计滤波器只能通过组合一种类型的单元滤波器（L10“）来自动获得期望的数字滤波器系数。此外，将对称数字序列{-1,0,9,16,9,0，-1} / 32在中心分成两部分，其中一个被用作非对称滤波器系数（H1至H3和H4 到H6）。这减少了所需的抽头的数量，消除了使用窗口功能，并且防止了所获得的滤波器特性中的离散化误差的产生。

12. 发明申请

WO2003077419A1 FINITE IMPULSE RESPONSE FILTER AND DIGITAL SIGNAL RECEIVING APPARATUS 审中-公开
标题翻译：有限冲突响应滤波器和数字信号接收装置
公开(公告)号：WO2003077419A1
公开(公告)日：2003-09-18
申请号：PCT/JP2003/003056
申请日：2003-03-14
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , YOMO, Hidekuni , KUNIEDA, Yoshinori , YAMAMOTO, Yuuri
发明人： YOMO, Hidekuni , KUNIEDA, Yoshinori , YAMAMOTO, Yuuri
IPC分类号： H03H17/06
CPC分类号： H03H17/0657 , H03H17/0223 , H03H17/0229 , H03H17/06 , H03H17/0621 , H03H2218/085
摘要： An A/D conversion section (101) performs oversampling on an analog signal at a rate M times the symbol rate to convert into digital signals. A FIR filtering section (102) has two delay-element sequences each with a plurality of delay elements, and the two sequences have different delay directions of input signal, i.e., forward direction and reverse direction. The delay directions of input signal can be switched, and according to the finite impulse response train having such delay-element sequences, convolutional calculation is performed. A phase determining section (103) determines a phase used in making a decision in a decision section (104). The decision section (104) makes a decision on a filtered signal using the phase determined in the phase determining section (103) to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with high accuracy without increasing the oversampling number, and performs fast calculation while having a reduced circuitry scale.
摘要翻译： A / D转换部（101）对符号率M倍的模拟信号进行过采样，以转换为数字信号。 FIR滤波部分（102）具有两个具有多个延迟元件的延迟元件序列，并且两个序列具有不同的输入信号的延迟方向，即正向和反向。可以切换输入信号的延迟方向，并且根据具有这种延迟元件序列的有限脉冲响应序列，进行卷积计算。相位确定部分（103）确定在判定部分（104）中作出决定所使用的相位。判定部（104）使用在相位确定部（103）中确定的相位对滤波后的信号进行判定，生成位数据。因此实现了一种数字信号接收装置，其在不增加过采样数量的情况下高精度地确定相位，并且在具有减小的电路规模的同时执行快速计算。

13. 发明申请

WO2002078245A1 TIMING SYNCHRONIZATION IN A COMMUNICATION DEVICE 审中-公开
标题翻译：通信设备中的时序同步
公开(公告)号：WO2002078245A1
公开(公告)日：2002-10-03
申请号：PCT/US2002/006628
申请日：2002-03-05
申请人： MOTOROLA, INC.
发明人： RINDERKNECHT, William, J. , SCHOOLER, Anthony , ANDREWS, Kevin, M. , KIM, Yun
IPC分类号： H04L7/00
CPC分类号： H04L7/0029 , H03H17/0286 , H03H17/0294 , H03H17/06 , H03H2017/0245 , H03H2218/12
摘要： A method for performing timing synchronization (fig. 3) between digital input data and a system clock in a communication device includes providing a system clock rate that is higher than a data clock rate (34) and sampling the input data at intervals in the system clock periods within the data clock period. The method includes adjusting (36 and 38) the timing between the digital input data and the system clock by either shortening the number of system clock periods and sampling intervals, or lengthening the number of system clock periods and sampling the input data at normal intervals and providing data insertion to fill one of the extra system clock periods, such that more data samples are provided in the data clock period.
摘要翻译：一种用于在通信设备中的数字输入数据和系统时钟之间执行定时同步（图3）的方法包括提供高于数据时钟速率（34）的系统时钟速率并且在系统中间隔地对输入数据进行采样数据时钟周期内的时钟周期。该方法包括通过缩短系统时钟周期和采样间隔的数量来调整（36和38）数字输入数据与系统时钟之间的定时，或延长系统时钟周期的数量，并以正常间隔对输入数据进行采样，提供数据插入以填充额外的系统时钟周期之一，使得在数据时钟周期中提供更多的数据样本。

14. 发明申请

WO2002076055A1 インターフェース回路审中-公开
标题翻译：接口电路
公开(公告)号：WO2002076055A1
公开(公告)日：2002-09-26
申请号：PCT/JP2002/000560
申请日：2002-01-25
申请人：株式会社日立製作所 , 齋藤達也 , 馬場貴成 , 勝康夫 , 山下寛樹
发明人：齋藤達也 , 馬場貴成 , 勝康夫 , 山下寛樹
IPC分类号： H04L25/03
CPC分类号： H04L25/0292 , H03H17/06 , H03K5/08 , H04L25/03 , H04L25/03878
摘要： An interface circuit (103) is integrated in an LSI. A comparator circuit (105) having a hysteresis characteristic compares the signal (111) outputted from a driver circuit (101) through a signal transmission line (102) with a signal (112) generated by passing the signal (111) through a delay circuit (104) so as to extract the temporal variation of the signal (111). The output signal (113) of the interface circuit (103) is at an H or L level depending on the temporal variation of the signal (111) and delivered to a receiver circuit (106). An FIR filter circuit subjects the output signal (111) from the signal transmit line and the signal (112) generated by passing the signal (111) through the delay circuit (104) to a waveform operation to restore a signal of H or L level. Even if the distortion of the signal waveform due to high-speed signal transmission in an LSI or between LSIs is great, the signal can be normally transmitted.
摘要翻译：接口电路（103）集成在LSI中。具有滞后特性的比较器电路（105）将通过信号传输线（102）从驱动电路（101）输出的信号（111）与通过信号（111）通过延迟电路产生的信号（112）进行比较（104），以便提取信号（111）的时间变化。接口电路（103）的输出信号（113）根据信号（111）的时间变化处于H或L电平，并被传送到接收器电路（106）。 FIR滤波器电路使来自信号传输线的输出信号（111）和通过延迟电路（104）传递信号（111）而产生的信号（112）进行波形操作，以恢复H或L电平的信号。即使由LSI或LSI之间的高速信号传输引起的信号波形的失真大，也能够正常地发送信号。

15. 发明申请

WO2002069492A2 SYSTEM AND METHOD FOR A HIGHLY-PROGRAMMABLE FIR FILTER 审中-公开
标题翻译：一种高可编程FIR滤波器的系统和方法
公开(公告)号：WO2002069492A2
公开(公告)日：2002-09-06
申请号：PCT/US2002/002093
申请日：2002-01-25
申请人： ANALOG DEVICES, INC.
发明人： SHAIKH, Ali, I.
IPC分类号： H03H17/06
CPC分类号： H03H17/0294 , H03H17/06
摘要： A highly-programmable Finite Impulse Response (FIR) digital filter overcomes the limitations of conventional configurations. Specifically, a compound FIR filter configuration is provided, offering the advantages of heightened programmability in both transfer function coefficients hf, hg and in degree of interpolation; distribution and sharing of resources between F and G filter portions, mode-switching capability between high-pass and low-pass modes, and programmable truncation/saturation.
摘要翻译：高度可编程有限脉冲响应（FIR）数字滤波器克服了常规配置的局限性。具体地说，提供了一种复合FIR滤波器结构，提供了传递函数系数hf，hg和内插程度两方面提高的可编程性的优点。 F和G滤波器部分之间的资源分配和共享，高通和低通模式之间的模式切换能力以及可编程截断/饱和。

16. 发明申请

WO02017486A1 METHOD FOR EFFICIENT AND ZERO LATENCY FILTERING IN A LONG IMPULSE RESPONSE SYSTEM 审中-公开
标题翻译：长时间反应系统中有效和零延迟滤波的方法
公开(公告)号：WO02017486A1
公开(公告)日：2002-02-28
申请号：PCT/SG2000/000125
申请日：2000-08-25
IPC分类号： H03H17/02 , H03H17/06
CPC分类号： H03H17/0219 , H03H17/0213 , H03H17/06
摘要： A method for long impulse response digital filtering of an input data stream, by use of a digital filtering system. Where the input data stream is divided into zero-input signals and zero-state signals. One of the zero-input signals and a corresponding impulse response of the digital filtering system is converted to the frequency domain to determine a respective zero-input response of the digital filtering system. One of the zero-state signals is convolved with a corresponding impulse response of the digital filtering system to determine a respective zero-state response of the digital filtering system, wherein at least part of the zero-input signal precedes the zero-state signal. The zero-state response of the digital filtering system is added to the zero-input response of the digital filtering system to determine the response of the digital filtering system. Apparatus for effecting this method is also disclosed.
摘要翻译：一种通过使用数字滤波系统对输入数据流进行长脉冲响应数字滤波的方法。其中输入数据流被分成零输入信号和零状态信号。零输入信号之一和数字滤波系统的相应脉冲响应被转换为频域以确定数字滤波系统的相应的零输入响应。其中一个零状态信号与数字滤波系统的对应的脉冲响应进行卷积，以确定数字滤波系统的相应的零状态响应，其中零输入信号的至少一部分在零状态信号之前。数字滤波系统的零状态响应被添加到数字滤波系统的零输入响应以确定数字滤波系统的响应。还公开了用于实现该方法的装置。

17. 发明申请

WO0143285A3 A RECONFIGURABLE FIR FILTER USING CSD COEFFICIENT REPRESENTATION 审中-公开
标题翻译：一种使用CSD系数表示的可重构FIR滤波器
公开(公告)号：WO0143285A3
公开(公告)日：2001-11-15
申请号：PCT/EP0012029
申请日：2000-11-30
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： WITTIG KARL
IPC分类号： H03H17/02 , H03H17/06
CPC分类号： H03H17/0294 , H03H17/0225 , H03H17/06
摘要： The present invention is directed to a reconfigurable finite impulse response (FIR) filter that processes data tap values with canonical sign digit (CSD) coefficients. The FIR filter according to the present invention includes a shift group associated with at least one of the data tap values and at least one of the CSD coefficients. Each shift group includes a plurality of parallel paths. Each parallel path shifts the data tap value according to a bit pair of the coefficient to produce a weighted product. An adder is also included that combines the weighted products from each of the shift groups.
摘要翻译：本发明涉及一种用规范符号数字（CSD）系数处理数据抽头值的可重新配置有限脉冲响应（FIR）滤波器。根据本发明的FIR滤波器包括与至少一个数据抽头值和至少一个CSD系数相关联的移位组。每个移位组包括多个平行路径。每个并行路径根据系数的比特对来移动数据抽头值以产生加权乘积。还包括一个加法器，它将来自每个换档组的加权产品组合在一起。

18. 发明申请

WO01022582A1 FIR FILTER UTILIZING PROGRAMMABLE SHIFTER 审中-公开
标题翻译： FIR滤波器利用可编程切换器
公开(公告)号：WO01022582A1
公开(公告)日：2001-03-29
申请号：PCT/US2000/022826
申请日：2000-08-18
IPC分类号： H03H17/02 , H03H17/06 , H03M3/02
CPC分类号： H03H17/06 , H03H17/0219
摘要： A circuit arrangement and method utilize a programmable shifter (48, 88) coupled downstream of a multiplier (36, 86) to shift the product of an input value and a pre-scaled filter coefficient that implements a predetermined filter function. Through the judicious selection of an appropriate pre-scaled filter coefficient and a shift distance to shift the product, truncation errors associated with a digital implementation of a filter may be minimized, offering improved filter response compared to other discrete filter implementations with like coefficient resolution, or in the alternative, permitting acceptable filter response to be maintained with reduced coefficient resolution. Moreover, where the coefficient resolution is reduced, a filter may be implemented using relatively less space, less power consumption and less delay than in comparable conventional designs.
摘要翻译：电路布置和方法利用耦合在乘法器（36,86）下游的可编程移位器（48,88）来移位输入值的乘积和实现预定滤波器功能的预定标滤波器系数。通过明智地选择适当的预缩放滤波器系数和移位距离来移位产品，与滤波器的数字实现相关联的截断误差可以最小化，与具有相似系数分辨率的其它离散滤波器实现相比，提供改进的滤波器响应，或者替代地，允许以降低的系数分辨率来维持可接受的过滤器响应。此外，在系数分辨率降低的情况下，可以使用相对较少的空间，更少的功率消耗和更少的延迟来实现与可比的常规设计相比的滤波器。

19. 发明申请

WO00046690A1 ECG WAVEFORM PROCESSING WITH REDUCED BASELINE WANDER 审中-公开
标题翻译：心电波波形加工与减少基线范围
公开(公告)号：WO00046690A1
公开(公告)日：2000-08-10
申请号：PCT/US2000/001883
申请日：2000-01-25
IPC分类号： A61B5/0428 , G06F17/00 , H03H17/02 , H03H17/06
CPC分类号： H03H17/06 , A61B5/0428 , H03H17/02
摘要： A baseline wander filter (BWF) with linear phase response for an ECG signal measuring system includes two cascaded box car FIR filters to estimate baseline wander. The cascaded box car filters form, in effect, a triangular FIR filter that generates a weighted sliding window average of the input samples to serve as the estimated baseline wander. The estimated baseline wander samples generated by the BWF are then substracted from the corresponding input ECG samples. The box car filters can be designed to avoid multiplication by adding the samples and dividing the resulting sum by the number of coefficients. By choosing the number of coefficients as a power of two, binary division can be performed by shifting the bits of the resulting sum to the right. Accordingly, the present invention avoids the relatively large computational load of conventional FIR filter-based systems. The BWF can be implemented in software in which each box car filter uses an accumulator data structure that generates the sum of the previous N samples. When adding the next sample to the sum, it substracts the Nth previous sample. The output sample of the BWF is equal to the value in the sum buffer, appropriately shifted.
摘要翻译：具有用于ECG信号测量系统的线性相位响应的基线漂移滤波器（BWF）包括两个级联的盒车FIR滤波器以估计基线漂移。级联盒式汽车滤波器实际上形成三角FIR滤波器，其产生输入样本的加权滑动窗口平均值，以用作估计的基线漂移。然后从相应的输入ECG样本中减去BWF产生的估计基线漂移样本。盒式汽车滤波器可以设计成避免乘以相加样本并将得到的和除以系数数。通过选择系数的数量作为2的幂，可以通过将所得和的位向右移位来执行二进制除法。因此，本发明避免了传统的基于FIR滤波器的系统的相对较大的计算量。 BWF可以在软件中实现，其中每个盒车滤波器使用产生先前N个样本的总和的累加器数据结构。将下一个样本添加到总和中时，它将减去第N个先前的样本。 BWF的输出样本等于和缓冲区中的值，适当偏移。

20. 发明申请

WO99018666A1 SIGNAL PROCESSOR WITH LOCAL SIGNAL BEHAVIOR 审中-公开
标题翻译：具有本地信号行为的信号处理器
公开(公告)号：WO99018666A1
公开(公告)日：1999-04-15
申请号：PCT/US1998/020651
申请日：1998-10-02
IPC分类号： G06F17/10 , H03F3/217 , H03H17/00 , H03H17/02 , H03H17/06 , H03H21/00 , H03M1/06 , H03M1/08 , H03M1/20 , H03M1/66
CPC分类号： H03M1/661 , G06F17/10 , H03F3/217 , H03H17/06 , H03M1/208
摘要： A new signal processing method and a signal processing engine which can achieve extremely fast responsiveness to instantaneous changes in the behavior of the signal, and maintain the accuracy of standard harmonic methods. The signal processing engine unifies Nyquist's theorem and Taylor's theorem by means of polynomial approximations using linear operators, e.g. differential and integral operators. The signal processing engine samples the signal at a rate which is n times the band limit of the signal, where n is greater than 2, i.e. greater than the Nyquist rate, produces a digital representation of the sampled signal, and calculates the outputs of linear operators applied to polynomial approximations of the sampled signal. A switch mode power amplifier which incorporates the signal processing method and engine of the overcomes shortcomings of existing switching amplifiers, e.g. class "D" amplifiers. These shortcomings include: poor handling of highly reactive complex loads (e.g., speakers), usually requiring a duty cycle or feed-back adjustment with the change of the load; poor performance in the upper part of the bandwidth, including numerous switching artifacts; and high distortion, especially in the upper part of the spectrum. These shortcomings are all overcome using the local signal behavior signal processing method and engine of the invention.
摘要翻译：一种新的信号处理方法和信号处理引擎，可以实现对信号行为的瞬时变化的极快响应，并保持标准谐波方法的准确性。信号处理引擎通过使用线性算子的多项式近似来统一奈奎斯特定理和泰勒定理，例如，差分和积分算子。信号处理引擎以n倍于信号频带限制的速率对信号进行采样，其中n大于2，即大于奈奎斯特速率，产生采样信号的数字表示，并计算线性的输出运算符应用于采样信号的多项式近似。一种开关模式功率放大器，其结合了克服现有开关放大器的缺点的信号处理方法和引擎，例如，类“D”放大器。这些缺点包括：高反应性复杂负载（例如扬声器）的处理不良，通常需要负载周期或负载的改变进行反馈调整; 在带宽的上部表现不佳，包括大量的切换伪影; 并且具有高失真，特别是在光谱的上部。这些缺点都使用本发明的本地信号行为信号处理方法和引擎来克服。

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