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11. 发明申请

WO01035224A1 BIT-SERIAL MEMORY ACCESS WITH WIDE PROCESSING ELEMENTS FOR SIMD ARRAYS 审中-公开
标题翻译：用于SIMD阵列的宽处理元件的位串行存储器访问
公开(公告)号：WO01035224A1
公开(公告)日：2001-05-17
申请号：PCT/US2000/041530
申请日：2000-10-25
IPC分类号： G06F15/173 , G06F15/80 , H04L29/06 , H04L29/08 , G06F12/08 , G06F15/00
CPC分类号： H04L67/1097 , G06F15/17337 , G06F15/17381 , G06F15/8023 , H04L29/06 , H04L69/329
摘要： A single-instruction multiple-data (SIMD) array processor (100) providing enhanced data transfer efficiency. The SIMD array processor includes at least one memory (102) such as a synchronous dynamic random access memory and a plurality of processing elements (104-134) configured in an array. Each processing element includes at least one "narrow" memory buffer and a plurality of "wide" data registers. The narrow memory buffer transfers data between the memory and at least one of the wide data registers while the processing element performs data processing operations. Each processing element further includes at least one parallel adder for adding data stored in the wide data registers coupled thereto, and a control circuit for controlling the memory buffer to transfer a data word stored in a selected data register between the memory and the selected data register.
摘要翻译：单指令多数据（SIMD）阵列处理器（100），提供增强的数据传输效率。 SIMD阵列处理器包括至少一个存储器（102），例如同步动态随机存取存储器和以阵列配置的多个处理元件（104-134）。每个处理元件包括至少一个“窄”存储器缓冲器和多个“宽”数据寄存器。窄处理器缓冲器在处理元件执行数据处理操作时，在存储器与宽数据寄存器中的至少一个之间传送数据。每个处理元件还包括至少一个并行加法器，用于将存储在与其耦合的宽数据寄存器中的数据相加，以及控制电路，用于控制存储器缓冲器以将存储在选择的数据寄存器中的数据字传输到存储器和所选择的数据寄存器。

12. 发明申请

WO01002975A1 NETWORK OF PARALLEL PROCESSORS FAULT-TOLERANT TOWARDS SAID PROCESSORS AND RECONFIGURATION METHOD APPLICABLE TO SUCH A NETWORK 审中-公开
标题翻译：并行处理器的网络故障处理器和适用于此网络的重新配置方法
公开(公告)号：WO01002975A1
公开(公告)日：2001-01-11
申请号：PCT/FR2000/001860
申请日：2000-06-30
IPC分类号： G06F11/00 , G06F15/80 , G06F11/20
CPC分类号： G06F11/2051 , G06F11/2025 , G06F11/2041 , G06F15/8023
摘要： The invention concerns a network of elementary parallel processors fault-tolerant towards said processors, comprising said elementary processors, additional elementary processors, elements interconnecting said processors and a control unit, and a succession of lines of interconnecting elements alternating with lines of processors, each processor being enclosed by four interconnecting elements, the lines of processors being lines of elementary processors, the last line of processors being a line of additional processors, the network onboard elements being interconnecting elements, wherein the control unit, connected to the processors and the interconnecting elements, sends instructions to the processors, controls the interconnecting elements, and verifies the integrity of said processors.
摘要翻译：本发明涉及对所述处理器容错的基本并行处理器的网络，包括所述基本处理器，附加的基本处理器，互连所述处理器的元件和控制单元以及与处理器线交替的一系列互连元件，每个处理器由四个互连元件围绕，处理器线是基本处理器线，最后一行处理器是附加处理器线，网络板载元件是互连元件，其中控制单元连接到处理器和互连元件向处理器发送指令，控制互连元件，并验证所述处理器的完整性。

13. 发明申请

WO9953411A3 MESH CONNECTED COMPUTER 审中-公开
标题翻译： MESH连接计算机
公开(公告)号：WO9953411A3
公开(公告)日：2000-04-20
申请号：PCT/US9904299
申请日：1999-04-09
申请人： LOCKHEED CORP
发明人： ABERCROMBIE ANDREW P , DUNCAN DAVID A , MEEKER WOODROW L , SCHOOMAKER RONALD W , VAN DYKE-LEWIS MICHELE D
IPC分类号： G06F15/80
CPC分类号： G06F9/3885 , G06F9/30145 , G06F9/30167 , G06F9/3887 , G06F15/8023
摘要： An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. In one aspect, each of the processing elements includes one or more addressable storage means and other elements arranged in a pipelined architecture. The controller includes means for receiving a high level instruction, and converting each instruction into a sequence of one or more processing element microinstructions for simultaneously controlling each stage of the processing element pipeline. In doing so, the controller detects and resolves a number of resource conflicts, and automatically generates instructions for registering image operands that are skewed with respect to one another in the processing element array. In another aspect, a programmer references images via pointers to image descriptors that include the actual addresses of various bits of multi-bit data. Other features facilitate and speed up the movement of data into and out of the apparatus. "Hit" detection and histogram logic are also included.
摘要翻译：用于处理数据的装置具有单指令多数据（SIMD）架构，以及提高性能和可编程性的许多特征。该装置包括处理元件的矩形阵列和控制器。在一个方面，每个处理元件包括一个或多个可寻址存储装置和以流水线架构布置的其他元件。控制器包括用于接收高电平指令的装置，并且将每个指令转换成一个或多个处理单元微指令的序列，以同时控制处理单元流水线的每一级。在这样做时，控制器检测并解决许多资源冲突，并且自动地生成用于登记在处理单元阵列中相对于彼此偏斜的图像操作数的指令。在另一方面，程序员通过指向包括多位数据的各种位的实际地址的图像描述符来引用图像。其他功能便于和加速数据进出设备的移动。还包括“Hit”检测和直方图逻辑。

14. 发明申请

WO9953412A9 GLOBAL INPUT/OUTPUT SUPPORT FOR A MESH CONNECTED COMPUTER 审中-公开
标题翻译：全球输入/输出支持连接计算机
公开(公告)号：WO9953412A9
公开(公告)日：2000-01-20
申请号：PCT/US9907001
申请日：1999-04-09
申请人： LOCKHEED CORP
发明人： ABERCROMBIE ANDREW P , SUTHA SURACHAI , HOLSZTYNSKI WLODZIMIERZ
IPC分类号： G06F15/80
CPC分类号： G06F15/8023
摘要： An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a pattern register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming "supercells" within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register. These registers have bit values corresponding to respective columns (for the X Pattern register) and rows (for the Y Pattern register) of the array. Patterns can be propagated from these registers into corresponding rows and columns. Further these registers can be used to receive values representing the logical OR of signals generated by individual PEs within respective rows and columns. Further, a number of global data registers are used to store information which can be broadcast back into the processing array.
摘要翻译：用于处理数据的装置具有单指令多数据（SIMD）架构，以及提高性能和可编程性的许多特征。该装置包括处理元件的矩形阵列和控制器。该装置提供用于移动阵列内的图像数据的多种技术。第一种技术，ROLL选项，同时在阵列内沿相反方向移动图像平面。第二种技术，门控移位选项使得对于每个PE，对于每个PE存储在模式寄存器中的值，将图像平面正常移位到相邻的PE。第三种技术是进位传播选项，将来自多个PE的计算结合起来，以便通过在阵列内形成“超级单元”来在n个时钟内完成n位操作。该装置还包括多位X模式寄存器和多位Y模式寄存器。这些寄存器具有对应于阵列的相应列（X模式寄存器）和行（Y模式寄存器）的位值。模式可以从这些寄存器传播到相应的行和列。此外，这些寄存器可以用于接收表示由相应行和列中的各PE产生的信号的逻辑或的值。此外，使用多个全局数据寄存器来存储可以广播回到处理阵列中的信息。

15. 发明申请

WO1996035997A1 PARALLEL PROCESSOR 审中-公开
标题翻译：并行处理器
公开(公告)号：WO1996035997A1
公开(公告)日：1996-11-14
申请号：PCT/RU1996000127
申请日：1996-05-22
申请人： YALESTOWN CORPORATION N.V. , BACHERIKOV, Gennady Ivanovich , GEVORKYAN, Viktor Ivanovich
发明人： YALESTOWN CORPORATION N.V.
IPC分类号： G06F15/80
CPC分类号： G06F15/8023
摘要： The invention is used in high-speed computer systems for processing high data flows in real time. The parallel processor comprises an initial load unit (7), a control unit (4), first and second buffer registers (2 and 3 respectively), permanent and operational storage devices (5 and 6 respectively), an address counter (8) and a matrix (17) of processor elements (1, 9-16) each of which is a matrix of similar computing cells. When a computer system is run on the proposed processor, a number of programs can be run simultaneously and with a high rate of exchange with memory units, other processor units and external devices. The processor can attain a speed of hundreds of billions of operations per second.
摘要翻译：本发明用于实时处理高数据流的高速计算机系统。并行处理器包括初始加载单元（7），控制单元（4），第一和第二缓冲寄存器（分别为2和3），永久和可操作存储设备（5和6），地址计数器（8）和处理器元件（1,9-16）的矩阵（17），每个处理器元件是类似计算单元的矩阵。当在所提出的处理器上运行计算机系统时，可以同时运行多个程序并以与存储器单元，其他处理器单元和外部设备的高速率交换。处理器每秒可以达到数百亿次的运行速度。

16. 发明申请

WO9417487A3 PARALLEL COMPUTER ARCHITECTURE AND CONFIGURATION PROCESS 审中-公开
标题翻译：并行计算机架构和配置过程
公开(公告)号：WO9417487A3
公开(公告)日：1994-10-13
申请号：PCT/EP9400218
申请日：1994-01-27
申请人： MAX PLANCK GESELLSCHAFT , MCCASKILL JOHN
发明人： MCCASKILL JOHN
IPC分类号： G06F15/80
CPC分类号： G06F15/8023
摘要： A parallel computer architecture and a process for building and reconfiguring a consecrated parallel computer for solving problems are disclosed. The process consists of a plurality of interconnected and dissociatable processes. This special computer architecture allows the end user by means of a new process to repetitively determine himself individual discrete processes in a small digital circuit and then to configure the whole computer with these interconnected processes, as easily as by compilation. Since the problem is then directly solved in parallel in the hardware, without the intermediate steps of an instruction set, problems may be solved up to one million times more quickly than in the fastest workstations. The building process makes use of commercially available chips and allows the end user to define a massive parallel computer adapted to his problems.

17. 发明申请

WO1994003852A1 ADVANCED MASSIVELY-PARALLEL COMPUTER APPARATUS 审中-公开
标题翻译：先进的并行计算机设备
公开(公告)号：WO1994003852A1
公开(公告)日：1994-02-17
申请号：PCT/US1993006524
申请日：1993-07-14
申请人： DAVID SARNOFF RESEARCH CENTER, INC.
发明人： DAVID SARNOFF RESEARCH CENTER, INC. , CHIN, Danny , PETERS, Joseph, Edward, Jr. , TAYLOR, Herbert, Hudson, Jr.
IPC分类号： G06F03/00
CPC分类号： G06F15/8023
摘要： The organization of a large (up to 8192 processors) massively -parallel computer apparatus (302) capable of teraop (i.e., of the order of 1012) computational rates and teraop data communication rate, in which its operating system includes means for providing the massively-parallel computer appparatus with multiuser time-shared operation is disclosed. Such massively-parallel computer apparatus is particularly suitable for real-time analysis of complex problems that require timely analysis include neural networks, volume visualization, and polygon rendering, as well as weather modeling, medical image, computer vision, molecular modeling and VLSI simulation.
摘要翻译：大型（高达8192个处理器）大容量并行计算机设备（302）的组织，其能够进行计算速率和teraop数据通信速率的teraop（即1012的量级），其中其操作系统包括用于大规模提供的装置公开了具有多用户时间共享操作的并行计算机设备。这种大规模并行的计算机装置特别适用于需要及时分析的复杂问题的实时分析，包括神经网络，体积可视化和多边形渲染，以及天气建模，医学图像，计算机视觉，分子建模和VLSI模拟。

18. 发明申请

WO8807722A3 IMPROVEMENTS IN OR RELATING TO CELLULAR ARRAY PROCESSING DEVICES 审中-公开
标题翻译：改进或相关于细胞阵列加工设备
公开(公告)号：WO8807722A3
公开(公告)日：1988-10-20
申请号：PCT/GB8800235
申请日：1988-03-28
申请人： STONEFIELD SYSTEMS PLC , CONSIDINE WILLIAM HOWARD
发明人： CONSIDINE WILLIAM HOWARD
IPC分类号： G06F15/80 , G06T5/20 , G06F15/06 , G06F7/48 , G06F15/68
CPC分类号： G06T5/20 , G06F15/8023
摘要： In each processing element of an array an input gate arrangement IG is provided with parallel AND-gates, holding register and ranking network which can be selected to provide outputs (derived from multiple bit neighbouring pixel values) for supply to either a generally conventional processing element PE2 or to a processing circuit PES which together with element PE2 forms an enhanced processing element. A bit summing network (11) in the circuit PES forms a count value signal representing the number of bits of a predetermined logic type supplied to inputs of the network (11), e.g. from the parallel AND-gates in arrangement IG. This count value signal is processed in adder (12) and accumulator (13) for example to form a convolution image value. The ranking network in the arrangement IG can be used to select for further processing a neighbouring pixel value of predetermined rank. Thus the components provided in circuit PES supplement the generally conventional element PE2 to enable simultaneous processing of a plurality of corresponding bits (same bit plane) of neighbouring pixel values so that convolutions and other image processing operations previously requiring inordinate time or hardware outlay are made economically possible at high speed. The components provided in device PES can be used in providing addition, substraction, multiplication and division operations as well as geometric transformations at enhanced speed.

19. 发明申请

WO2016170312A1 DATA PROCESSOR 审中-公开
标题翻译：数据处理器
公开(公告)号：WO2016170312A1
公开(公告)日：2016-10-27
申请号：PCT/GB2016/051076
申请日：2016-04-19
申请人： ADAPTIVE ARRAY SYSTEMS LIMITED
发明人： SHENTON, Christopher , NAVEN, Finbar
IPC分类号： G06F15/80
CPC分类号： G06F15/8023 , G06F9/3885
摘要： A data processor is described which comprises a sequence of processing stages, each processing stage comprising a plurality of processing elements, each processing element comprising an arithmetic logic unit, one or more input data buffers and one or more output data buffers, the arithmetic logic unit being operable to conduct a data processing operation on one or more values stored in an input data buffer and to store the result of the data processing operation into an output data buffer. Between each pair of processing stages in the sequence, an interconnect is provided, for conveying data values stored in the output data buffers of the processing elements in a first one of the processing stages in the pair to the input data buffers of the processing elements in the next processing stage in the pair. A controller is provided, which is operable to specify, in respect of each processing stage, a data processing operation to be carried out by the processing elements in that processing stage, and to specify, in respect of each interconnect, a routing from one or more of the output data buffers of one or more of the processing elements of the processing stage from which the interconnect is receiving data to one or more of the input data buffers of one or more of the processing elements of the processing stage to which the interconnect is conveying data.
摘要翻译：描述了一种数据处理器，其包括一系列处理级，每个处理级包括多个处理元件，每个处理元件包括算术逻辑单元，一个或多个输入数据缓冲器和一个或多个输出数据缓冲器，算术逻辑单元可操作地对存储在输入数据缓冲器中的一个或多个值进行数据处理操作，并将数据处理操作的结果存储到输出数据缓冲器中。在序列中的每对处理阶段之间，提供互连，用于将处理元件的输出数据缓冲器中的第一个处理级中的数据值传送到处理元件的输入数据缓冲器该对的下一个处理阶段。提供了一种控制器，其可操作以针对每个处理阶段来指定要由该处理阶段中的处理元件执行的数据处理操作，并且针对每个互连来指定来自一个或多个处理级的一个或多个处理元件的输出数据缓冲器中的多个输出数据缓冲器，互连器从该处理元件接收数据到处理级的一个或多个处理元件的一个或多个输入数据缓冲器中的互连正在传送数据。

20. 发明申请

WO2014085975A1 可动态重构的多级并行单指令多数据阵列处理系统审中-公开
公开(公告)号：WO2014085975A1
公开(公告)日：2014-06-12
申请号：PCT/CN2012/085814
申请日：2012-12-04
申请人：中国科学院半导体研究所
发明人：石匆 , 吴南健 , 龙希田 , 杨杰 , 秦琦
IPC分类号： G06F9/38
CPC分类号： G06K9/6251 , G06F15/8023 , G06K9/00986 , G06N3/0454 , G06N3/063 , G06T1/20
摘要：本发明公开了一种可动态重构的多级并行单指令多数据阵列处理系统，包括像素级并行的处理单元PE阵列和行并行的行处理器RP阵列，其中PE阵列主要完成低、中级图像处理中适于以全像素并行执行的线性运算部分，而RP阵列完成低、中级处理中适合以行并行方式完成的运算或者较复杂的非线性运算。特别地，PE阵列还能以极小的性能和面积开销，动态重构为二维自组织映射SOM神经网络，该神经网络可以在RP的配合下实现高速并行在线训练和特征识别等高级图像处理功能，彻底克服了在现有可编程视觉芯片和并行视觉处理器中像素级并行处理阵列无法用于高级图像处理的缺陷，促进了功能完整的低成本、低功耗、智能便携式高速实时片上视觉图像系统的实现。

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