专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

WO2007098024A2 ALLOCATION OF RESOURCES AMONG AN ARRAY OF COMPUTERS 审中-公开
标题翻译：计算机阵列资源分配
公开(公告)号：WO2007098024A2
公开(公告)日：2007-08-30
申请号：PCT/US2007/004081
申请日：2007-02-16
申请人： TECHNOLOGY PROPERTIES LIMITED , MOORE, Charles, H.
发明人： MOORE, Charles, H.
IPC分类号： G06F15/16
CPC分类号： G06F15/8023 , G06F9/321 , G06F9/325
摘要： A computer array (10) has a plurality of computers (12). The computers (12) communicate directly with neighbor computers and indirectly with other computers in the array. The computers pass data words that include data and/or instructions. As many as 4 instructions can be included in one 18 bit data word. Since four instructions are communicated at a time it is possible to communicate an entire micro-loop made up of as many as four instructions. The computers of the present invention can execute instruction directly from their input registers.
摘要翻译：计算机阵列（10）具有多个计算机（12）。计算机（12）与邻近计算机直接通信，并与阵列中的其他计算机间接通信。计算机传递包括数据和/或指令的数据字。一个18位数据字中可以包含多达4条指令。由于一次通信四个指令，所以可以传达由多达四个指令组成的整个微环路。本发明的计算机可以直接从其输入寄存器执行指令。

12. 发明申请

WO2007098006A2 EXECUTION OF INSTRUCTIONS DIRECTLY FROM INPUT SOURCE 审中-公开
标题翻译：从输入源直接执行指令
公开(公告)号：WO2007098006A2
公开(公告)日：2007-08-30
申请号：PCT/US2007/004030
申请日：2007-02-16
申请人： TECHNOLOGY PROPERTIES LIMITED , MOORE, Charles, H.
发明人： MOORE, Charles, H.
IPC分类号： G06F15/16
CPC分类号： G06F15/8007 , G06F1/32 , G06F9/30134 , G06F9/325 , G06F9/3802 , G06F9/3885
摘要： A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions/the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise have required an interrupt of an otherwise active computer.
摘要翻译：计算机阵列（10）具有多个计算机（12）。计算机（12）以异步方式彼此通信，并且计算机（12）本身以内部的大致异步方式进行操作。当一台计算机（12）尝试与另一台计算机（12）进行通信时，它将进入睡眠状态，直到另一台计算机（12）准备完成交易，从而节省电力并减少热量产生。休眠计算机（12）可以等待数据或指令（12）。在指令/睡眠计算机（12）可以等待存储指令或立即执行指令的情况下。在后一种情况下，在首先将指令首先置于存储器中之前，将指令置于指令寄存器（30a）中，当它们被接收和执行时，它们被放置在指令寄存器（30a）中。指令可以包括能够重复执行一系列操作的微循环（100）。在一个应用中，休眠计算机（12）被输入唤醒，使得它开始了否则将需要另外活动的计算机的中断的动作。

13. 发明申请

WO2013066381A2 DECORATIVE PANELS WITH RECESSED PATTERNS AND METHODS OF MAKING THE SAME WITH A FLEXIBLE DIE 审中-公开
标题翻译：带有凹凸图案的装饰面板及其制造方法与柔性模具
公开(公告)号：WO2013066381A2
公开(公告)日：2013-05-10
申请号：PCT/US2012/026157
申请日：2012-02-22
申请人： HUNTER DOUGLAS INDUSTRIES SWITZERLAND GMBH , MOORE, Charles, H. , SUTTON, Matthew, T. , WILLHAM, John, E.C. , BREWSTER, M., Hoyt
发明人： MOORE, Charles, H. , SUTTON, Matthew, T. , WILLHAM, John, E.C. , BREWSTER, M., Hoyt
CPC分类号： B44C5/04 , B29C59/02 , B29K2101/12 , B29L2007/001 , Y10T428/24355
摘要： Implementations of the present invention relate to decorative thermoplastic resin panels, which can include one or more recesses. The recess of the thermoplastic resin panels can have texture or texture patterns that differ from the texture or texture patterns of non-recessed portions or other recesses of the decorative thermoplastic resin panel. Additionally, the present invention relates to a method for forming recesses in thermoplastic panels with a flexible die.
摘要翻译：本发明的实施方案涉及装饰性热塑性树脂板，其可以包括一个或多个凹部。热塑性树脂板的凹部可以具有不同于装饰热塑性树脂板的非凹部或其他凹部的质地或纹理图案的纹理或纹理图案。此外，本发明涉及一种用于在具有柔性模具的热塑性面板中形成凹部的方法。

14. 发明申请

WO2009128924A3 METHOD AND APPARATUS FOR SERIALIZING AND DESERIALIZING 审中-公开
公开(公告)号：WO2009128924A3
公开(公告)日：2009-10-22
申请号：PCT/US2009/002361
申请日：2009-04-15
申请人： VNS PORTFOLIO LLC , MOORE, Charles, H. , BAILEY, Gregory, V.
发明人： MOORE, Charles, H. , BAILEY, Gregory, V.
IPC分类号： G06F9/46 , G06F12/02 , G06F13/38
摘要： A method and apparatus for serialization of a transmitted data stream and deserialization of data on a single die chip 105, including a plurality of processors 110 on a single chip 105. The processors on the chip 105 are connected by single drop busses 120 and act as individual processors with at least some dedicated memory 118. The method of serializing includes initialization of a register serializing a most significant bit from said register, moving all bits in the direction of the most significant bit, replacing the least significant bit with a value of zero, and continuing said serializing and moving steps are continued until a stopping condition is met. The method of deserialization of a data word includes initializing a register used for deserialization, deserializing a bit, positioning the bit in the least significant bit of the register, moving all bits in the direction of the most significant bit, and continuing the positioning and moving steps until a stopping condition is reached.

15. 发明申请

WO2009128922A2 METHOD AND APPARATUS FOR COMPUTER MEMORY 审中-公开
标题翻译：计算机存储器的方法和装置
公开(公告)号：WO2009128922A2
公开(公告)日：2009-10-22
申请号：PCT/US2009/002359
申请日：2009-04-15
申请人： VNS PORTFOLIO LLC , MOORE, Charles, H.
发明人： MOORE, Charles, H.
IPC分类号： G06F12/00
CPC分类号： G11C5/025 , G11C5/02 , G11C8/14 , Y10T29/49002
摘要： A method and apparatus for forming computer memory 10 including RAM, ROM, Stacks and other registers. The memory array 10 includes a number of individual memory cells 40, 42, 44, 46 connected to each other by word lines 18, 20 and bit lines 30, 32. Memory cells 40, 42, 44, 46 word lines 18, 20 and bit lines 30, 32 are orented in a manner to provide minimum line length and a substantialy square geometery. The method includes arranging the memory cells in an interleaved formation.
摘要翻译：一种用于形成包括RAM，ROM，堆叠和其他寄存器的计算机存储器10的方法和装置。存储器阵列10包括通过字线18,20和位线30,32彼此连接的多个单独存储单元40,42,44,46。存储单元40,42,44,46字线18,20和位线30,32以提供最小线长度和实质方形几何形状的方式。该方法包括将存储器单元布置成交错地层。

16. 发明申请

WO2009042112A2 SHIFT-ADD BASED MULTIPLICATION 审中-公开
标题翻译：基于移位添加的乘法
公开(公告)号：WO2009042112A2
公开(公告)日：2009-04-02
申请号：PCT/US2008/011005
申请日：2008-09-23
申请人： VNS PORTFOLIO LLC , MOORE, Charles, H.
发明人： MOORE, Charles, H.
IPC分类号： G06F7/52
CPC分类号： G06F7/582
摘要： A system for multiplication of multi-bit first and second values. A processor is provided that has first and second memories with bit-positions that can all be zero or one and where the first memory has a low bit (LB). The first value is arranged in the first memory so its LSB is in the first memory LB, and the remaining bit-positions in the first memory are set to zero. The second value is arranged in the second memory such that its LSB is in the bit- position of the second memory that is next higher in order than the MSB of the first value in the first memory, and the remaining bit-positions in the second memory are set to zero. A +* operation is then performed a quantity of times equaling the number of significant bits in the first value, inclusive, thus obtaining the product of the first and second values.
摘要翻译：
用于多位第一和第二值相乘的系统。提供了一种具有第一和第二存储器的处理器，其中第一和第二存储器的位位置可以全部为零或一，并且第一存储器具有低位（LB）。第一个值被安排在第一个存储器中，因此它的LSB位于第一个存储器LB中，并且第一个存储器中的其余位位置为零。第二值被安排在第二存储器中，使得它的LSB处于第二存储器的比特位置，第二存储器的顺序比第一存储器中的第一值的MSB次高，并且第二存储器中的剩余比特位置内存设置为零。然后执行一个等于包含第一个值的有效位数的次数的操作，从而得到第一个和第二个值的乘积。

17. 发明申请

WO2008118343A1 ANALOG-TO-DIGITAL CONVERTER SYSTEM WITH INCREASED SAMPLING FREQUENCY 审中-公开
标题翻译：具有增加采样频率的模数转数转换器系统
公开(公告)号：WO2008118343A1
公开(公告)日：2008-10-02
申请号：PCT/US2008/003693
申请日：2008-03-20
申请人： VNS PORTFOLIO LLC , MOORE, Charles, H. , SNIVELY, Leslie, O. , HUIE, John
发明人： MOORE, Charles, H. , SNIVELY, Leslie, O. , HUIE, John
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H03M1/1215 , H03M1/60
摘要： The present invention is an improvement in sampling a high frequency input analog signal and converting it to a digital output signal. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using a different ADC for each sampling, wherein each sampling is sequentially offset a certain amount of time from the most recent preceding sampling. The samplings from the multitude of ADCs are combined to form a single contiguous digital output signal. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a specified permittivity material device, and a sequencer or multiplier.
摘要翻译：本发明是对高频输入模拟信号进行采样并将其转换为数字输出信号的改进。这是通过使用多个模数转换器与分布式采样系统结合来实现的。多个转换器和分布式采样系统的组合允许使用诸如0.18微米硅的常规器件处理，并且还提供非常高频率的输入信号的精确采样。分布式采样系统通过对每个采样使用不同的ADC来提供输入信号的多次采样，其中每个采样从最近的先前采样顺序地偏移一定量的时间。来自多个ADC的采样被组合以形成单个相邻的数字输出信号。分布式采样系统的类型包括串联互连的多个细长迹线图案，指定的介电常数材料器件和定序器或乘法器。

18. 发明申请

WO2012158472A2 ARCHITECTURAL PANELS INCLUDING ELONGATED THERMOPLASTIC MEMBERS AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：包括长寿命热塑性构件的建筑面板及其制造方法
公开(公告)号：WO2012158472A2
公开(公告)日：2012-11-22
申请号：PCT/US2012/037382
申请日：2012-05-10
申请人： HUNTER DOUGLAS INDUSTRIES SWITZERLAND GMBH , SUTTON, Matthew, T. , WILLHAM, JOHN, E.C. , MOORE, Charles, H.
发明人： SUTTON, Matthew, T. , WILLHAM, JOHN, E.C. , MOORE, Charles, H.
CPC分类号： E04C2/20 , B29C43/02 , Y10T428/18 , Y10T428/24802
摘要： Implementations of the present invention relate to for incorporating virgin or recycled thermoplastic resin materials into architectural thermoplastic panels that have ordered and reproducible geometric patterns. More specifically, at least one implementation provides a method for fusing thermoplastic elongated members, such as circular rods and rectangular bars, sourced from recycled thermoplastic resin to form the architectural thermoplastic panels.
摘要翻译：本发明的实施方案涉及将未加工或再循环的热塑性树脂材料结合到具有有序和可再现的几何图案的建筑热塑性板中。更具体地，至少一个实施方案提供了一种用于熔化源自再循环热塑性树脂的热塑性细长构件（例如圆形棒和矩形棒）以形成建筑热塑性面板的方法。

19. 发明申请

WO2011115992A3 LAMINATE PANELS PRODUCED FROM BIOPOLYMERS 审中-公开
公开(公告)号：WO2011115992A3
公开(公告)日：2011-09-22
申请号：PCT/US2011/028524
申请日：2011-03-15
申请人： HUNTER DOUGLAS INDUSTRIES B.V. , MOORE, Charles, H. , WILLHAM, John, E.C.
发明人： MOORE, Charles, H. , WILLHAM, John, E.C.
IPC分类号： B32B27/06 , B32B9/04 , B32B37/00
摘要： A method for manufacturing the biopolymer panel may include positioning a plurality of biopolymer sheets adjacent to one another, and subjecting them to a laminating temperature that exceeds the glass-transition temperature of the sheets for a time period sufficient to achieve lamination. The laminate panel is then quenched at a quenching temperature that is below the glass-transition temperature. The time period during lamination, as well as any "rest" period between lamination and quenching, is sufficiently short so as to prevent clouding or hazing as a result of crystallization of the biopolymer resin materials. In addition, the panel exhibits sufficient flame retardency to meet applicable building codes, exhibits sufficient impact resistance for use as a decorative or structural panel building material, and exhibits no substantial thermally induced degradation as a result of subjection to the laminating temperature. The panels may be used as decorative or structural building materials.

20. 发明申请

WO2010056369A2 METHOD AND APPARATUS FOR CIRCUIT SIMULATION 审中-公开
标题翻译：用于电路仿真的方法和设备
公开(公告)号：WO2010056369A2
公开(公告)日：2010-05-20
申请号：PCT/US2009/006149
申请日：2009-11-17
申请人： VNS PORTFOLIO LLC , MOORE, Charles, H.
发明人： MOORE, Charles, H.
IPC分类号： H01L21/66 , H01L21/02
CPC分类号： G06F17/5022
摘要： A method of preparing a circuit simulator, said method comprising initializing a normalized adjusted gate voltage value. Then performing the steps of determining a normalized adjusted gate voltage datum in dependence upon the initial normalized adjusted gate voltage value. Storing the normalized adjusted gate voltage datum at a memory address in a one- dimensional array based on the normalized adjusted gate voltage. Decrementing the normalized adjusted gate voltage value by a predetermined decrement amount. And verifying the decremented gate voltage value. Then repeating until a stop gate voltage value is reached.
摘要翻译：一种制备电路模拟器的方法，所述方法包括初始化归一化的调整的栅极电压值。然后执行根据初始归一化调整栅极电压值确定归一化调整栅极电压数据的步骤。基于归一化的调整后的栅极电压将归一化的调整的栅极电压数据存储在一维阵列中的存储器地址处。将归一化的调整的栅极电压值减少预定的减量。并验证递减的栅极电压值。然后重复，直到达到停止栅极电压值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式