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11. 发明申请

WO2009095902A2 SYSTEMS AND METHODS FOR HANDLING IMMEDIATE DATA ERRORS IN FLASH MEMORY 审中-公开
标题翻译：用于处理闪存中立即数据错误的系统和方法
公开(公告)号：WO2009095902A2
公开(公告)日：2009-08-06
申请号：PCT/IL2008/001237
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , LEVY, Shmuel
发明人： WEINGARTEN, Hanan , LEVY, Shmuel
IPC分类号： G06F11/27
CPC分类号： G11C16/3463 , G06F11/1072 , G11C11/5628 , G11C16/14 , G11C16/3404 , G11C16/3413 , G11C16/3454 , G11C16/3486 , G11C29/00 , G11C2211/5621
摘要： A flash memory system comprising temporary memory, writing apparatus for writing first logical data from the temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors, reading apparatus for reading the physical representation from the cells, thereby to generate, and store in the temporary memory, second logical data which if read immediately is identical to the first logical data other than the known errors; and controlling apparatus controlling the writing apparatus and the reading apparatus and including known error ID apparatus operative to identify the known errors by comparing the first logical data to second logical data read immediately after the physical representation is generated, to store information characterizing the known errors and to use the information, when the second logical data is next read, to correct the known errors.
摘要翻译：一种闪存系统，包括临时存储器，用于将来自临时存储器的第一逻辑数据写入具有至少两个级别的闪存单元的写入装置，从而生成包括已知错误的第一逻辑数据的物理表示，用于读取物理从而生成并存储在临时存储器中的第二逻辑数据，其如果立即读取与已知错误以外的第一逻辑数据相同; 以及控制装置和控制装置，并且包括已知的错误ID装置，其可操作以通过将第一逻辑数据与生成物理表示之后立即读取的第二逻辑数据进行比较来识别已知错误，以存储表征已知错误的信息，以及使用该信息，当第二逻辑数据被下一次读取时，以校正已知错误。

12. 发明申请

WO2009074979A3 CHIEN-SEARCH SYSTEM EMPLOYING A CLOCK-GATING SCHEME TO SAVE POWER FOR ERROR CORRECTION DECODER AND OTHER APPLICATIONS 审中-公开
公开(公告)号：WO2009074979A3
公开(公告)日：2009-06-18
申请号：PCT/IL2008/001235
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , STERIN, Eli , KANTER, Ofir, Avraham
发明人： WEINGARTEN, Hanan , STERIN, Eli , KANTER, Ofir, Avraham
IPC分类号： H03M13/00
摘要： Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising a sequence of functional units each operative to compute a corresponding term in the sequence of terms included in the error locator polynomial, each term having a degree; and a power saving unit operative to de-activate at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank.

13. 发明申请

WO2009072103A2 FLASH MEMORY APPARATUS AND METHODS USING A PLURALITY OF DECODING STAGES INCLUDING OPTIONAL USE OF CONCATENATED BCH CODES AND/OR DESIGNATION OF "FIRST BELOW" CELLS 审中-公开
标题翻译：闪存存储器装置和使用多个解码阶段的方法，包括可选择使用固定的BCH代码和/或指定“第一个”单元格
公开(公告)号：WO2009072103A2
公开(公告)日：2009-06-11
申请号：PCT/IL2008001233
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD , WEINGARTEN HANAN , LEVY SHMUEL , KATZ MICHAEL
发明人： WEINGARTEN HANAN , LEVY SHMUEL , KATZ MICHAEL
IPC分类号： G06F12/02
CPC分类号： G06F11/1044 , G06F11/1068 , G11C11/5621 , G11C11/5692 , G11C29/00
摘要： A method for decoding a plurality of flash memory cells which are error-correction-coded as a unit, the method comprising providing a hard-decoding success indication indicating whether or not hard-decoding is at least likely to be successful; and soft-decoding the plurality of flash memory cells at a first resolution only if the hard-decoding success indication indicates that the hard-decoding is not at least likely to be successful.
摘要翻译：一种用于对作为单元进行纠错编码的多个闪存单元进行解码的方法，所述方法包括提供硬解码成功指示，指示硬解码是否至少可能成功; 以及仅当所述硬解码成功指示指示所述硬解码最不可能成功时，以所述第一分辨率对所述多个闪存单元进行软解码。

14. 发明申请

WO2009053963A2 METHODS FOR ADAPTIVELY PROGRAMMING FLASH MEMORY DEVICES AND FLASH MEMORY SYSTEMS INCORPORATING SAME 审中-公开
标题翻译：用于适应性编程FLASH存储器件的方法和包含其的闪存存储器系统
公开(公告)号：WO2009053963A2
公开(公告)日：2009-04-30
申请号：PCT/IL2008/001242
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , SABBAG, Erez , KATZ, Michael
发明人： WEINGARTEN, Hanan , SABBAG, Erez , KATZ, Michael
IPC分类号： G06F7/74
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2211/5621 , G11C2211/5641
摘要： A method for programming a plurality of data sequences into a corresponding plurality of flash memory functional units using a programming process having at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, the method comprising providing at least one indication of at least one varying situational characteristic and determining a value for said at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, for each flash memory functional unit, depending at least partly on said indication of said varying characteristic; and, for each individual flash memory functional unit from among said plurality of flash memory functional units, programming a sequence of bits into said individual flash memory functional unit using a programming process having at least one selectable parameter, said at least one selectable parameter being set at said value determined for said individual flash memory functional unit.
摘要翻译：一种用于使用编程处理将多个数据序列编程到相应的多个闪速存储器功能单元中的方法，所述编程处理具有控制给定数据序列的编程过程的持续时间的至少一个可选择的编程持续时间控制参数，所述方法包括提供至少一个变化的情境特征的指示，并且至少部分地基于每个闪存功能单元确定用于所述至少一个可选择的编程持续时间控制参数的值，用于控制给定数据序列的编程过程的持续时间所述指示所述变化的特征; 并且对于来自所述多个闪存功能单元的每个单独的闪速存储器功能单元，使用具有至少一个可选参数的编程处理将一系列比特编程到所述单独闪存功能单元中，所述至少一个可选参数被设置以所述个别闪存功能单元确定的所述值。

15. 发明申请

WO2009053961A2 SYSTEMS AND METHODS FOR MULTIPLE CODING RATES IN FLASH DEVICES 审中-公开
标题翻译： FLASH设备中多种编码速率的系统和方法
公开(公告)号：WO2009053961A2
公开(公告)日：2009-04-30
申请号：PCT/IL2008/001228
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , KATZ, Michael
发明人： WEINGARTEN, Hanan , KATZ, Michael
IPC分类号： G06F7/74
CPC分类号： G06F11/1068 , G11C29/82 , G11C2029/0411
摘要： A system and method for encoding information arriving from a host in order to store the coded information in flash memory, the method comprising encoding information arriving from a host for storage at a flash memory location including generating a number of redundancy bytes, the encoding proceeding at an encoding rate which is a function of the number of redundancy bytes generated, the encoding including determining an effective error rate, including an anticipated rate of expected reading errors, for the flash memory location; and selecting the encoding rate as a function of the effective error rate such that the number of redundancy bytes is sufficient to overcome the anticipated rate of expected reading errors with a predetermined degree of certainty.
摘要翻译：一种用于编码从主机到达的信息以便将编码信息存储在闪速存储器中的信息的系统和方法，所述方法包括编码从主机到达的信息，以在闪速存储器位置存储，包括生成多个冗余字节，编码步骤所述编码速率是所生成的冗余字节数的函数，所述编码包括确定对于所述闪存位置的预期读取错误率的有效误差率; 并且选择编码率作为有效误码率的函数，使得冗余字节数足以以预定的确定程度克服预期读取错误的预期速率。

16. 发明申请

WO2009072100A3 SYSTEMS AND METHODS FOR TEMPORARILY RETIRING MEMORY PORTIONS 审中-公开
标题翻译：用于临时退火记忆部分的系统和方法
公开(公告)号：WO2009072100A3
公开(公告)日：2010-03-04
申请号：PCT/IL2008001230
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD , WEINGARTEN HANAN , LEVY SHMUEL , KATZ MICHAEL
发明人： WEINGARTEN HANAN , LEVY SHMUEL , KATZ MICHAEL
IPC分类号： G06F13/10
CPC分类号： G06F12/0246 , G06F2212/1032 , G11C16/349
摘要： Flash memory apparatus including a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during the first duration of time, only to the certain portions, thereby to define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for the first duration of time.
摘要翻译：包括多个存储器部分的闪速存储装置以及在第一持续时间内至少在第一持续时间内仅保留来自所述多个存储器部分中的某些部分包括分配数据的操作的操作的控制器，仅限于某些部分，从而将多个存储部分中的至少一个除了某些部分之外，作为第一持续时间的退休存储器部分。

17. 发明申请

WO2009053963A3 METHODS FOR ADAPTIVELY PROGRAMMING FLASH MEMORY DEVICES AND FLASH MEMORY SYSTEMS INCORPORATING SAME 审中-公开
标题翻译：用于适应性编程FLASH存储器件的方法和包含其的闪存存储器系统
公开(公告)号：WO2009053963A3
公开(公告)日：2010-03-04
申请号：PCT/IL2008001242
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD , WEINGARTEN HANAN , SABBAG EREZ , KATZ MICHAEL
发明人： WEINGARTEN HANAN , SABBAG EREZ , KATZ MICHAEL
IPC分类号： G06F9/26
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2211/5621 , G11C2211/5641
摘要： A method for programming a plurality of data sequences into a corresponding plurality of flash memory functional units using a programming process having at least one selectable programming duration-controlling parameter, the method comprising providing at least one indication of at least one varying situational characteristic and determining a value for said at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, for each flash memory functional unit, depending at least partly on said indication of said varying characteristic; and, for each individual flash memory functional unit from among said plurality of flash memory functional units, programming a sequence of bits into said individual flash memory functional unit using a programming process having at least one selectable parameter, said at least one selectable parameter being set at said value determined for said individual flash memory functional unit.
摘要翻译：一种用于使用具有至少一个可编程持续时间控制参数的编程处理将多个数据序列编程成相应的多个闪速存储器功能单元的方法，所述方法包括提供至少一个变化的情景特征和确定至少部分地基于所述变化特性的所述指示，为所述至少一个可选择的编程持续时间控制参数控制针对每个快闪存储器功能单元的给定数据序列的编程过程的持续时间的值; 并且对于来自所述多个闪存功能单元的每个单独的闪速存储器功能单元，使用具有至少一个可选参数的编程处理将一系列比特编程到所述单独闪存功能单元中，所述至少一个可选参数被设置以所述个别闪存功能单元确定的所述值。

18. 发明申请

WO2009053961A3 SYSTEMS AND METHODS FOR MULTIPLE CODING RATES IN FLASH DEVICES 审中-公开
标题翻译：闪存器件中多种编码速率的系统和方法
公开(公告)号：WO2009053961A3
公开(公告)日：2010-03-04
申请号：PCT/IL2008001228
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD , WEINGARTEN HANAN , KATZ MICHAEL
发明人： WEINGARTEN HANAN , KATZ MICHAEL
IPC分类号： H04L12/28
CPC分类号： G06F11/1068 , G11C29/82 , G11C2029/0411
摘要： A system and method for encoding information arriving from a host in order to store the coded information in flash memory, the method comprising encoding information arriving from a host for storage at a flash memory location including generating a number of redundancy bytes, the encoding proceeding at an encoding rate which is a function of the number of redundancy bytes generated, the encoding including determining an effective error rate, including an anticipated rate of expected reading errors, for the flash memory location; and selecting the encoding rate as a function of the effective error rate such that the number of redundancy bytes is sufficient to overcome the anticipated rate of expected reading errors with a predetermined degree of certainty.
摘要翻译：一种用于编码从主机到达的信息以便将编码信息存储在闪速存储器中的信息的系统和方法，所述方法包括编码从主机到达的信息以在闪速存储器位置存储，包括生成多个冗余字节，编码步骤所述编码速率是所生成的冗余字节数的函数，所述编码包括确定包括闪存存储器位置的预期读取错误的预期速率的有效错误率; 并且选择编码率作为有效错误率的函数，使得冗余字节的数量足以以预定的确定程度克服预期读取错误的预期速率。

19. 发明申请

WO2009078006A2 APPARATUS FOR CODING AT A PLURALITY OF RATES IN MULTI-LEVEL FLASH MEMORY SYSTEMS, AND METHODS USEFUL IN CONJUNCTION THEREWITH 审中-公开
标题翻译：用于在多级闪速存储器系统中的多个速率进行编码的装置，以及与之相关的方法
公开(公告)号：WO2009078006A2
公开(公告)日：2009-06-25
申请号：PCT/IL2008/001243
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , LEVY, Shmuel , BAR, Ilan
发明人： WEINGARTEN, Hanan , LEVY, Shmuel , BAR, Ilan
IPC分类号： G06F12/02
CPC分类号： G11C16/10 , G06F11/1072 , G11C7/1006 , G11C11/5628 , G11C29/00 , G11C29/028 , G11C29/50 , G11C2029/0411 , G11C2029/5002
摘要： A method and system for writing in flash memory, the system operative for, and the method comprising, writing data onto a plurality of logical pages characterized by a plurality of different probabilities of error respectively, the writing including encoding data intended for each of the plurality of physical pages using a redundancy code with a different code rate for each individual physical page, the code rate corresponding to the probability of error in the individual logical page.
摘要翻译：一种写入闪速存储器的方法和系统，该系统的操作方法和方法包括：将数据分别写入多个不同的误差概率的多个逻辑页面上，该写入包括用于多个不同的错误概率的编码数据的物理页面使用具有针对每个单独物理页面的不同代码率的冗余代码，该代码速率对应于各个逻辑页面中的错误概率。

20. 发明申请

WO2009074979A2 CHIEN-SEARCH SYSTEM EMPLOYING A CLOCK-GATING SCHEME TO SAVE POWER FOR ERROR CORRECTION DECODER AND OTHER APPLICATIONS 审中-公开
标题翻译：采用时钟校正方式的CHIEN-SEARCH系统，用于保存错误校正解码器和其他应用的电源
公开(公告)号：WO2009074979A2
公开(公告)日：2009-06-18
申请号：PCT/IL2008001235
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD , WEINGARTEN HANAN , STERIN ELI , KANTER OFIR AVRAHAM
发明人： WEINGARTEN HANAN , STERIN ELI , KANTER OFIR AVRAHAM
IPC分类号： G06F11/10
CPC分类号： H03M13/1545 , H03M13/1515 , H03M13/152
摘要： Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising a sequence of functional units each operative to compute a corresponding term in the sequence of terms included in the error locator polynomial, each term having a degree; and a power saving unit operative to de-activate at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank.
摘要翻译： Chien搜索装置用于评估具有已知秩的错误定位多项式，并且包括其有限域中的每个元素的项的序列，其元素分别对应于要解码的数据块流中的每一个中的位，所述装置包括序列每个功能单元各自操作以计算包括在误差定位器多项式中的项序列中的对应项，每个项具有度; 以及功率节省单元，其用于从所述功能单元序列中去激活至少一个单独的功能单元，所述单个功能单元在活动时可操作，以计算其度数超过所述等级的项。

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