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1. 发明申请

WO2009078006A2 APPARATUS FOR CODING AT A PLURALITY OF RATES IN MULTI-LEVEL FLASH MEMORY SYSTEMS, AND METHODS USEFUL IN CONJUNCTION THEREWITH 审中-公开
标题翻译：用于在多级闪速存储器系统中的多个速率进行编码的装置，以及与之相关的方法
公开(公告)号：WO2009078006A2
公开(公告)日：2009-06-25
申请号：PCT/IL2008/001243
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , LEVY, Shmuel , BAR, Ilan
发明人： WEINGARTEN, Hanan , LEVY, Shmuel , BAR, Ilan
IPC分类号： G06F12/02
CPC分类号： G11C16/10 , G06F11/1072 , G11C7/1006 , G11C11/5628 , G11C29/00 , G11C29/028 , G11C29/50 , G11C2029/0411 , G11C2029/5002
摘要： A method and system for writing in flash memory, the system operative for, and the method comprising, writing data onto a plurality of logical pages characterized by a plurality of different probabilities of error respectively, the writing including encoding data intended for each of the plurality of physical pages using a redundancy code with a different code rate for each individual physical page, the code rate corresponding to the probability of error in the individual logical page.
摘要翻译：一种写入闪速存储器的方法和系统，该系统的操作方法和方法包括：将数据分别写入多个不同的误差概率的多个逻辑页面上，该写入包括用于多个不同的错误概率的编码数据的物理页面使用具有针对每个单独物理页面的不同代码率的冗余代码，该代码速率对应于各个逻辑页面中的错误概率。

2. 发明申请

WO2009072100A2 SYSTEMS AND METHODS FOR TEMPORARILY RETIRING MEMORY PORTIONS 审中-公开
标题翻译：用于临时退火记忆部分的系统和方法
公开(公告)号：WO2009072100A2
公开(公告)日：2009-06-11
申请号：PCT/IL2008/001230
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , LEVY, Shmuel , KATZ, Michael
发明人： WEINGARTEN, Hanan , LEVY, Shmuel , KATZ, Michael
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1032 , G11C16/349
摘要： Flash memory apparatus including a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during the first duration of time, only to the certain portions, thereby to define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for the first duration of time.
摘要翻译：包括多个存储器部分的闪速存储装置以及在第一持续时间内至少在第一持续时间内仅保留来自所述多个存储器部分中的某些部分包括分配数据的操作的操作的控制器，，仅限于某些部分，从而将多个存储部分中的至少一个除了某些部分之外，作为第一持续时间的退休存储器部分。

3. 发明申请

WO2009072104A3 FLASH MEMORY DEVICE WITH PHYSICAL CELL VALUE DETERIORATION ACCOMMODATION AND METHODS USEFUL IN CONJUNCTION THEREWITH 审中-公开
公开(公告)号：WO2009072104A3
公开(公告)日：2009-06-11
申请号：PCT/IL2008/001239
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , LEVY, Shmuel , KATZ, Michael
发明人： WEINGARTEN, Hanan , LEVY, Shmuel , KATZ, Michael
IPC分类号： G06F9/26
摘要： A method for determining thresholds useful for converting cell physical levels into cell logical values in an array of digital memory cells storing physical levels which diminish over time, the method comprising determining extent of deterioration of the physical levels and determining thresholds accordingly for at least an individual cell in said array; and reading the individual cell including reading a physical level in the cell and converting the physical level into a logical value using the thresholds, wherein the determining comprises storing predefined physical levels rather than data-determined physical levels in each of a plurality of cells and computing extent of deterioration by determining deterioration of the predefined physical levels.

4. 发明申请

WO2009072103A3 FLASH MEMORY APPARATUS AND METHODS USING A PLURALITY OF DECODING STAGES INCLUDING OPTIONAL USE OF CONCATENATED BCH CODES 审中-公开
公开(公告)号：WO2009072103A3
公开(公告)日：2009-06-11
申请号：PCT/IL2008/001233
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , LEVY, Shmuel , KATZ, Michael
发明人： WEINGARTEN, Hanan , LEVY, Shmuel , KATZ, Michael
IPC分类号： G11C8/00
摘要： A method for decoding a plurality of flash memory cells which are error-correction-coded as a unit, the method comprising providing a hard-decoding success indication indicating whether or not hard-decoding is at least likely to be successful; and soft-decoding the plurality of flash memory cells at a first resolution only if the hard-decoding success indication indicates that the hard-decoding is not at least likely to be successful.

5. 发明申请

WO2009095902A2 SYSTEMS AND METHODS FOR HANDLING IMMEDIATE DATA ERRORS IN FLASH MEMORY 审中-公开
标题翻译：用于处理闪存中立即数据错误的系统和方法
公开(公告)号：WO2009095902A2
公开(公告)日：2009-08-06
申请号：PCT/IL2008/001237
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , LEVY, Shmuel
发明人： WEINGARTEN, Hanan , LEVY, Shmuel
IPC分类号： G06F11/27
CPC分类号： G11C16/3463 , G06F11/1072 , G11C11/5628 , G11C16/14 , G11C16/3404 , G11C16/3413 , G11C16/3454 , G11C16/3486 , G11C29/00 , G11C2211/5621
摘要： A flash memory system comprising temporary memory, writing apparatus for writing first logical data from the temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors, reading apparatus for reading the physical representation from the cells, thereby to generate, and store in the temporary memory, second logical data which if read immediately is identical to the first logical data other than the known errors; and controlling apparatus controlling the writing apparatus and the reading apparatus and including known error ID apparatus operative to identify the known errors by comparing the first logical data to second logical data read immediately after the physical representation is generated, to store information characterizing the known errors and to use the information, when the second logical data is next read, to correct the known errors.
摘要翻译：一种闪存系统，包括临时存储器，用于将来自临时存储器的第一逻辑数据写入具有至少两个级别的闪存单元的写入装置，从而生成包括已知错误的第一逻辑数据的物理表示，用于读取物理从而生成并存储在临时存储器中的第二逻辑数据，其如果立即读取与已知错误以外的第一逻辑数据相同; 以及控制装置和控制装置，并且包括已知的错误ID装置，其可操作以通过将第一逻辑数据与生成物理表示之后立即读取的第二逻辑数据进行比较来识别已知错误，以存储表征已知错误的信息，以及使用该信息，当第二逻辑数据被下一次读取时，以校正已知错误。

6. 发明申请

WO2009074978A2 SYSTEMS AND METHODS FOR ERROR CORRECTION AND DECODING ON MULTI-LEVEL PHYSICAL MEDIA 审中-公开
标题翻译：用于多级物理介质的错误校正和解码的系统和方法
公开(公告)号：WO2009074978A2
公开(公告)日：2009-06-18
申请号：PCT/IL2008/001229
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan
发明人： WEINGARTEN, Hanan
IPC分类号： A61K36/8962
CPC分类号： H03M13/19 , A61K36/8962 , G06F11/1008 , G06F11/1048 , H03M13/6566
摘要： Apparatus and methods for operating a flash device characterized by use of Lee distance based codes in a flash device so as to increase the number of errors that can be corrected for a given number of redundancy cells, compared with Hamming distance based codes.
摘要翻译：用于操作闪存设备的装置和方法，其特征在于在闪存设备中使用基于Lee距离的代码，以便与基于汉明距离的代码相比，增加对于给定数量的冗余单元可以校正的错误的数量。

7. 发明申请

WO2009072105A3 A LOW POWER CHIEN-SEARCH BASED BCH/RS DECODING SYSTEM FOR FLASH MEMORY 审中-公开
公开(公告)号：WO2009072105A3
公开(公告)日：2009-06-11
申请号：PCT/IL2008/001241
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , STERIN, Eli , KANTER, Ofir, Avraham , KATZ, Michael
发明人： WEINGARTEN, Hanan , STERIN, Eli , KANTER, Ofir, Avraham , KATZ, Michael
IPC分类号： G11C16/04
摘要： A low power Chien searching method employing Chien search circuitry comprising at least two hardware components that compute at least two corresponding bits comprising a Chien search output, the method comprising activating only a subset of the hardware components thereby to compute only a subset of the bits of the Chien search output; and activating hardware components other than those in the subset of hardware components, to compute additional bits of the Chien search output other than the bits in the subset of bits, only if a criterion on the subset of the bits of the Chien search output is satisfied.

8. 发明申请

WO2009053962A3 SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS 审中-公开
公开(公告)号：WO2009053962A3
公开(公告)日：2009-04-30
申请号：PCT/IL2008/001238
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan
发明人： WEINGARTEN, Hanan
IPC分类号： G06F13/00
摘要： A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

9. 发明申请

WO2009037697A2 IMPROVED SYSTEMS AND METHODS FOR DETERMINING LOGICAL VALUES OF COUPLED FLASH MEMORY CELLS 审中-公开
标题翻译：用于确定耦合闪存存储器单元的逻辑值的改进系统和方法
公开(公告)号：WO2009037697A2
公开(公告)日：2009-03-26
申请号：PCT/IL2008/001234
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan
发明人： WEINGARTEN, Hanan
IPC分类号： G11C7/20
CPC分类号： G11C11/5642 , G11C2211/5634
摘要： Systems and methods for determining program levels useful for reading cells of a flash memory, such as but not limited to detecting charge levels for the cells, obtaining joint conditional probability densities for a plurality of combinations of program levels of the cells; and determining program levels for the cells respectively such that an aggregated joint probability value of the joint conditional probability densities is maximized.
摘要翻译：用于确定用于读取闪速存储器的单元的程序级的系统和方法，例如但不限于检测单元的电荷水平，为单元的程序级的多个组合获得联合条件概率密度; 以及分别确定所述小区的节目级别，使得联合条件概率密度的聚合联合概率值最大化。

10. 发明申请

WO2009074979A3 CHIEN-SEARCH SYSTEM EMPLOYING A CLOCK-GATING SCHEME TO SAVE POWER FOR ERROR CORRECTION DECODER AND OTHER APPLICATIONS 审中-公开
公开(公告)号：WO2009074979A3
公开(公告)日：2009-06-18
申请号：PCT/IL2008/001235
申请日：2008-09-17
申请人： DENSBITS TECHNOLOGIES LTD. , WEINGARTEN, Hanan , STERIN, Eli , KANTER, Ofir, Avraham
发明人： WEINGARTEN, Hanan , STERIN, Eli , KANTER, Ofir, Avraham
IPC分类号： H03M13/00
摘要： Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising a sequence of functional units each operative to compute a corresponding term in the sequence of terms included in the error locator polynomial, each term having a degree; and a power saving unit operative to de-activate at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank.

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