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11. 发明申请

WO2007130320A2 CONCEALMENT OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION 审中-公开
标题翻译：电子设计自动化信息隐藏
公开(公告)号：WO2007130320A2
公开(公告)日：2007-11-15
申请号：PCT/US2007/010379
申请日：2007-04-30
申请人： MENTOR GRAPHICS CORPORATION , PIKUS, Fedor, G.
发明人： PIKUS, Fedor, G.
IPC分类号： G06F20060101 , G06F9/45
CPC分类号： G06F17/5081 , G06F21/6209 , G06F21/6227 , G09C5/00 , H04L9/0863 , H04L9/321
摘要： An electronic design automation tool may receive information related to electronic design automation that contains secured information, such as physically secured information, and annotations to indicate the secured portions of the information. Upon receiving such information, the electronic design automation tool may identify those portions of the information comprising secured information related to electronic design automation, and unlock the secured information for processing. The electronic design automation tool may process at least some of the secured electronic design automation information without revealing that secured information to unauthorized persons, tools, systems, or otherwise compromising the protection of that secured information. That is, the design automation tool may process the secured electronic design automation information so that the secured information is concealed both while it is being processed and by the output information generated from processing the secured information.
摘要翻译：电子设计自动化工具可以接收与电子设计自动化有关的信息，其中包含安全信息，例如物理安全信息和注释，以指示信息的安全部分。电子设计自动化工具在接收到这样的信息时，可以识别包括与电子设计自动化相关的安全信息的信息的那些部分，并且解锁用于处理的安全信息。电子设计自动化工具可以处理至少一些安全的电子设计自动化信息，而不向未经授权的人员，工具，系统或其他方式泄漏安全信息，从而损害对该安全信息的保护。也就是说，设计自动化工具可以处理安全的电子设计自动化信息，使得安全信息在被处理时被隐藏，并且由处理安全信息产生的输出信息。

12. 发明申请

WO2005078528A2 SOURCE OPTIMIZATION FOR IMAGE FIDELITY AND THROUGHPUT 审中-公开
标题翻译：源图像优化和图像优化
公开(公告)号：WO2005078528A2
公开(公告)日：2005-08-25
申请号：PCT/US2005/002091
申请日：2005-01-21
申请人： MENTOR GRAPHICS CORPORATION
发明人： GRANIK, Yuri
IPC分类号： G03F7/20
CPC分类号： G03F7/70491 , G03F7/70108 , G03F7/70441 , G03F7/705
摘要： A system and method for optimizing an illumination source to print a desired pattern of features dividing a light source into pixels and determining an optimum intensity for each pixel such that when the pixels are simultaneously illuminated, the error in a printed pattern of features is minimized. In one embodiment, pixel solutions are constrained from solutions that are bright, continuous, and smooth. In another embodiment, the light source optimization and resolution enhancement technique(s) are iteratively performed to minimize errors in a printed pattern of features.
摘要翻译：一种用于优化照明源以打印将光源分成像素并且为每个像素确定最佳强度的特征的特征图案的系统和方法，使得当像素同时被照亮时，特征的印刷图案中的误差被最小化。在一个实施例中，像素解决方案受限于明亮，连续和平滑的解决方案。在另一个实施例中，迭代地执行光源优化和分辨率增强技术以最小化特征的打印图案中的错误。

13. 发明申请

WO2004046866A2 AUTOMATED REPARTITIONING OF HARDWARE AND SOFTWARE COMPONENTS IN AN EMBEDDED SYSTEM 审中-公开
标题翻译：嵌入式系统中硬件和软件组件的自动化分配
公开(公告)号：WO2004046866A2
公开(公告)日：2004-06-03
申请号：PCT/US2003/036638
申请日：2003-11-13
申请人： MENTOR GRAPHICS CORPORATION , KLEIN, Russell, Alan
发明人： KLEIN, Russell, Alan
IPC分类号： G06F
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A hardware-software system design optimization tool is described. The tool allows a designer to optimize the system performance by allowing him to select software components of the system and move them to a hardware representation. The software components are selected by using a performance profile of the system, which comprises time data related to execution of the software components, memory and bus transactions. In another aspect, the tool automatically collects the performance data and generates the performance profile. In another aspect, performance data is collected by modeling the execution of the hardware-software system. In another aspect, hardware-software system is modeled again after selected software components are moved to a hardware representation to inquire whether the move improved overall system performance.
摘要翻译：描述了硬件 - 软件系统设计优化工具。该工具允许设计者通过允许他选择系统的软件组件并将其移动到硬件表示来优化系统性能。通过使用系统的性能配置文件来选择软件组件，其包括与执行软件组件，存储器和总线事务相关的时间数据。另一方面，该工具自动收集性能数据并生成性能配置文件。在另一方面，通过建模硬件 - 软件系统的执行来收集性能数据。另一方面，在将选定的软件组件移动到硬件表示之后，再次对硬件 - 软件系统进行建模，以查询移动是否提高了整体系统性能。

14. 发明申请

WO2003050726A1 PARALLEL ELECTRONIC DESIGN AUTOMATION: SHARED SIMULTANEOUS EDITING 审中-公开
标题翻译：并行电子设计自动化：共享同步编辑
公开(公告)号：WO2003050726A1
公开(公告)日：2003-06-19
申请号：PCT/US2002/039394
申请日：2002-12-10
申请人： MENTOR GRAPHICS CORPORATION
发明人： PFEIL, Charles , SMITH, Edwin, Franklin , PETUNIN, Vladimir , POTTS, Henry , NATARAJAN, Venkat
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , G06F2217/74
摘要： A method to simultaneously allow multiple users connected to multiple clients (202, 204, 206) to make an edit request (300) to edit in shared areas of a master design including displaying the master design, allowing a first user to edit in a shared area of the design, simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design.
摘要翻译：一种同时允许连接到多个客户端（202,204,206）的多个用户进行编辑请求（300）以在主设计的共享区域中编辑的方法，包括显示主设计，允许第一用户在共享中编辑同时允许第二用户在设计的共享区域中编辑，同时保持设计的完整性。

15. 发明申请

WO2003043057A3 SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS 审中-公开
公开(公告)号：WO2003043057A3
公开(公告)日：2003-05-22
申请号：PCT/US2002/036342
申请日：2002-11-12
申请人： MENTOR GRAPHICS CORPORATION , SUAYA, Roberto , ESCOVAR, Rafael
发明人： SUAYA, Roberto , ESCOVAR, Rafael
IPC分类号： G06F17/50
摘要： A method of optimizing the propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed . The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires. The disclose method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedance at the junctions between the branches are substantially equal.

16. 发明申请

WO2020214195A1 METHOD AND APPARATUS FOR PROCESSING MEMORY REPAIR INFORMATION 审中-公开
公开(公告)号：WO2020214195A1
公开(公告)日：2020-10-22
申请号：PCT/US2019/048223
申请日：2019-08-27
申请人： MENTOR GRAPHICS CORPORATION
发明人： NADEAU-DOSTIE, Benoit , ROMAIN, Luc
IPC分类号： G11C29/00 , G11C29/44 , G11C29/40
摘要： Systems and methods for repairing a memory. A method includes performing a repair analysis of the embedded memories to produce repair information. The method includes storing the repair information in the registers, where the registers are organized into groups having chains of identical length. The method includes performing collision detection between the repair information in each of the groups. The method includes merging the repair information in each of the groups. The method includes repairing the embedded memories using the merged repair information.

17. 发明申请

WO2020162979A1 DIE YIELD ASSESSMENT BASED ON PATTERN-FAILURE RATE SIMULATION 审中-公开
公开(公告)号：WO2020162979A1
公开(公告)日：2020-08-13
申请号：PCT/US2019/047839
申请日：2019-08-23
申请人： MENTOR GRAPHICS CORPORATION
发明人： KIM, Young Chang , STURTEVANT, John L. , BURBINE, Andrew , CLIFFORD, Christopher
IPC分类号： G06F17/50 , G03F1/36 , G03F7/20
摘要： This application discloses a computing system to identify structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data and to generate process windows for the identified structures based, at least in part, on the mask layout data and a failure definition for the identified structures. The computing system utilizes process windows for the identified structures to determine failure rates for the identified structures based on a distribution of the manufacturing parameters. The computing system determines frequency of occurrences for the identified structures from the mask layout data and generates a die yield metric for the integrated circuit by aggregating the failure rates for the identified structures based on the frequency of occurrences for the identified structures in the integrated circuit. These increases in yield of the integrated circuit allow manufacturers to produce more units per fixed processing cost of the wafer.

18. 发明申请

WO2014145877A2 CLOUD SERVICES PLATFORM 审中-公开
标题翻译：云服务平台
公开(公告)号：WO2014145877A2
公开(公告)日：2014-09-18
申请号：PCT/US2014/030717
申请日：2014-03-17
申请人： MENTOR GRAPHICS CORPORATION
发明人： BENCHORIN, Shay , PETIT, Emmanuel , LEEF, Serge
CPC分类号： H04L41/50 , G06F3/0488 , G06F3/1203 , G06F3/1226 , G06F3/126 , G06F3/1287 , G06F3/1292 , G06Q10/101 , G06Q10/103 , G06Q30/0207 , G06Q30/0237 , H04L12/2818 , H04L29/08099 , H04L29/08567 , H04N21/43615
摘要： Embodiments of the disclosed technology comprise a cloud-hosted central service platform that interfaces and enables access to both central and distributed resources and peripherals for connected mobile applications. For example, this platform allows service providers and application developers to create a large number of new classes of applications, leveraging web access to devices, sensors, and/or actuators of any kind. This platform can be applied to virtually any vertical segment. Any of the disclosed features or aspects of the disclosed embodiments can be used in various combinations and subcombinations with one another or with other methods, apparatus, and systems.
摘要翻译：所公开的技术的实施例包括云托管的中央服务平台，该云托管的中央服务平台接口并允许访问连接的移动应用的中央和分布式资源和外围设备。例如，该平台允许服务提供商和应用程序开发人员创建大量新类别的应用程序，利用对任何类型的设备，传感器和/或执行器的Web访问。该平台可应用于几乎任何垂直分段。所公开的实施例的任何所公开的特征或方面可以以彼此或与其他方法，装置和系统的各种组合和子组合来使用。

19. 发明申请

WO2011059439A2 SCAN TEST APPLICATION THROUGH HIGH-SPEED SERIAL INPUT/OUTPUTS 审中-公开
标题翻译：通过高速串行输入/输出进行扫描测试
公开(公告)号：WO2011059439A2
公开(公告)日：2011-05-19
申请号：PCT/US2009/064251
申请日：2009-11-12
申请人： MENTOR GRAPHICS CORPORATION , RAJSKI, Janusz , MUKHERJEE, Nilanjan , KASSAB, Mark, A. , RINDERKNECHT, Thomas, H. , DESSOUKY, Mohamed
发明人： RAJSKI, Janusz , MUKHERJEE, Nilanjan , KASSAB, Mark, A. , RINDERKNECHT, Thomas, H. , DESSOUKY, Mohamed
IPC分类号： G01R31/3185
CPC分类号： G01R31/318572 , G01R31/318547

20. 发明申请

WO2010099124A1 NETLIST SYNTHESIS USING MULTIPLE SYNTHESIS CONFIGURATIONS 审中-公开
标题翻译：使用多种合成配置的网络列表综合
公开(公告)号：WO2010099124A1
公开(公告)日：2010-09-02
申请号：PCT/US2010/025104
申请日：2010-02-23
申请人： MENTOR GRAPHICS CORPORATION , PLATZKER, Daniel, M. , MITRA, Pankaj , VALS, Alexander
发明人： PLATZKER, Daniel, M. , MITRA, Pankaj , VALS, Alexander
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed herein are representative embodiments of methods, systems, and apparatus for performing synthesis. For example, in one exemplary method disclosed herein, a high-level description of a complete circuit design is partitioned into a plurality of sections. Two or more synthesis engine configurations are selected for a respective one of the sections. The respective one of the sections is synthesized using the two or more selected synthesis engine configurations, thereby generating two or more gate-level descriptions. A gate-level description of the complete circuit design is generated that includes at least a portion of one of the gate-level descriptions. Computer-readable media storing instructions for causing a computer to perform any of the disclosed methods are also disclosed herein.
摘要翻译：这里公开了用于执行合成的方法，系统和装置的代表性实施例。例如，在本文公开的一个示例性方法中，将完整电路设计的高级描述划分为多个部分。对于相应的一个部分选择两个或多个合成引擎配置。使用两个或更多个选择的合成引擎配置来合成各个部分中的相应一个部分，从而产生两个或多个门级描述。生成完整电路设计的门级描述，其包括门级描述之一的至少一部分。存储用于使计算机执行任何所公开的方法的指令的计算机可读介质也在本文中公开。

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